From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECC69C4360C for ; Fri, 11 Oct 2019 01:42:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C75B421920 for ; Fri, 11 Oct 2019 01:42:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728011AbfJKBmC (ORCPT ); Thu, 10 Oct 2019 21:42:02 -0400 Received: from mga05.intel.com ([192.55.52.43]:59416 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727751AbfJKBmC (ORCPT ); Thu, 10 Oct 2019 21:42:02 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2019 18:42:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,282,1566889200"; d="scan'208";a="198555052" Received: from unknown (HELO localhost) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 10 Oct 2019 18:42:00 -0700 Date: Fri, 11 Oct 2019 09:43:54 +0800 From: Yang Weijiang To: Jim Mattson Cc: Yang Weijiang , kvm list , LKML , Paolo Bonzini , Sean Christopherson , "Michael S. Tsirkin" , Radim =?utf-8?B?S3LEjW3DocWZ?= Subject: Re: [PATCH v7 4/7] KVM: VMX: Load Guest CET via VMCS when CET is enabled in Guest Message-ID: <20191011014354.GA11176@local-michael-cet-test> References: <20190927021927.23057-1-weijiang.yang@intel.com> <20190927021927.23057-5-weijiang.yang@intel.com> <20191009064339.GC27851@local-michael-cet-test> <20191010013027.GA1196@local-michael-cet-test.sh.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.3 (2019-02-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 10, 2019 at 04:44:17PM -0700, Jim Mattson wrote: > On Wed, Oct 9, 2019 at 6:28 PM Yang Weijiang wrote: > > > > On Wed, Oct 09, 2019 at 04:08:50PM -0700, Jim Mattson wrote: > > > On Tue, Oct 8, 2019 at 11:41 PM Yang Weijiang wrote: > > > > > > > > On Wed, Oct 02, 2019 at 11:54:26AM -0700, Jim Mattson wrote: > > > > > On Thu, Sep 26, 2019 at 7:17 PM Yang Weijiang wrote: > > > > > > + if (cet_on) > > > > > > + vmcs_set_bits(VM_ENTRY_CONTROLS, > > > > > > + VM_ENTRY_LOAD_GUEST_CET_STATE); > > > > > > > > > > Have we ensured that this VM-entry control is supported on the platform? > > > > > > > > > If all the checks pass, is it enought to ensure the control bit supported? > > > > > > I don't think so. The only way to check to see if a VM-entry control > > > is supported is to check the relevant VMX capability MSR. > > > > > It's a bit odd, there's no relevant CET bit in VMX cap. MSR, so I have > > to check like this. > > Bit 52 of the IA32_VMX_ENTRY_CTLS MSR (index 484H) [and bit 52 of the > IA32_VMX_TRUE_ENTRY_CTLS MSR (index 490H), on hardware that supports > the "true" VMX capability MSRs] will be 1 if it is legal to set bit 20 > of the VM-entry controls field to 1. > Oh, you meant this, I'll add the check, thanks. > > > BTW, what about the corresponding VM-exit control? > > The kernel supervisor mode CET is not implemented yet, so I don't load host CET > > states on VM-exit, in future, I'll add it. > > If you don't clear the supervisor mode CET state on VM-exit and the > guest has set IA32_S_CET.SH_STK_EN, doesn't that mean that > supervisor-mode shadow stacks will then be enabled on the host after > VM-exit? Yeah, I should clear the MSR on VM-exit before supervisor-mode is implemented. Thank you! BTW, I'll move this bit-set before VM-entry, vmx_set_cr4() is not a suitable place to set the bit.