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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m14sm799068otl.26.2019.10.17.12.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 12:03:10 -0700 (PDT) Date: Thu, 17 Oct 2019 14:03:10 -0500 From: Rob Herring To: Xiaowei Bao Cc: Zhiqiang.Hou@nxp.com, bhelgaas@google.com, mark.rutland@arm.com, shawnguo@kernel.org, leoyang.li@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, Minghuan.Lian@nxp.com, andrew.murray@arm.com, mingkai.hu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape Message-ID: <20191017190310.GA32063@bogus> References: <20191015083702.21792-1-xiaowei.bao@nxp.com> <20191015083702.21792-3-xiaowei.bao@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191015083702.21792-3-xiaowei.bao@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 15, 2019 at 04:36:58PM +0800, Xiaowei Bao wrote: > Add the documentation for the Device Tree binding of the layerscape > PCIe GEN4 controller with EP mode. > > Signed-off-by: Xiaowei Bao > --- > v2: > - remove the status entry in EP Example. > > .../bindings/pci/layerscape-pcie-gen4.txt | 27 +++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt > index b40fb5d..06f9309 100644 > --- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt > +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt > @@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller > This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all > the common properties defined in mobiveil-pcie.txt. > > +HOST MODE > +========= > Required properties: > - compatible: should contain the platform identifier such as: > "fsl,lx2160a-pcie" > @@ -23,7 +25,20 @@ Required properties: > - msi-parent : See the generic MSI binding described in > Documentation/devicetree/bindings/interrupt-controller/msi.txt. > > -Example: > +DEVICE MODE > +========= > +Required properties: > +- compatible: should contain the platform identifier such as: > + "fsl,lx2160a-pcie-ep" > +- reg: base addresses and lengths of the PCIe controller register blocks. > + "regs": PCIe controller registers. > + "addr_space" EP device CPU address. > +- apio-wins: number of requested apio outbound windows. > + > +Optional Property: > +- max-functions: Maximum number of functions that can be configured (default 1). > + > +RC Example: > > pcie@3400000 { > compatible = "fsl,lx2160a-pcie"; > @@ -50,3 +65,13 @@ Example: > <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; > }; > + > +EP Example: > + > + pcie_ep@3400000 { To repeat my previous comment: pcie-endpoint@... > + compatible = "fsl,lx2160a-pcie-ep"; > + reg = <0x00 0x03400000 0x0 0x00100000 > + 0x80 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + apio-wins = <8>; > + }; > -- > 2.9.5 >