* [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640
@ 2019-10-21 5:13 Bjorn Andersson
2019-10-21 5:13 ` [PATCH 01/11] arm64: dts: qcom: db820c: Move non-soc entries out of /soc Bjorn Andersson
` (11 more replies)
0 siblings, 12 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Refactor msm8996 and db820c in order to make it follow the structure of newer
platforms, move db820c specific things to db820c.dtsi and then introduce the
Informace 6640 Single Board Computer.
Bjorn Andersson (11):
arm64: dts: qcom: db820c: Move non-soc entries out of /soc
arm64: dts: qcom: msm8996: Use node references in db820c
arm64: dts: qcom: msm8996: Move regulator consumers to db820c
arm64: dts: qcom: msm8996: Move regulators to db820c
arm64: dts: qcom: db820c: Group root nodes
arm64: dts: qcom: db820c: Sort all nodes
arm64: dts: qcom: db820c: Remove pin specific files
arm64: dts: qcom: msm8996: Pad addresses
arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi
arm64: dts: qcom: db820c: Use regulator names from schematics
arm64: dts: qcom: msm8996: Introduce IFC6640
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/apq8096-db820c-pins.dtsi | 109 -
.../dts/qcom/apq8096-db820c-pmic-pins.dtsi | 92 -
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 1416 ++++---
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 412 ++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 3505 ++++++++---------
6 files changed, 2982 insertions(+), 2553 deletions(-)
delete mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
delete mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
--
2.23.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 01/11] arm64: dts: qcom: db820c: Move non-soc entries out of /soc
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 02/11] arm64: dts: qcom: msm8996: Use node references in db820c Bjorn Andersson
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
The USB id pins and wlan regulator are not platform devices, so move
them out of /soc
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 58 ++++++++++----------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index dba3488492f1..da2f01eb3be2 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -399,13 +399,6 @@
};
};
- usb3_id: usb3-id {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb3_vbus_det_gpio>;
- };
-
usb@76f8800 {
status = "okay";
extcon = <&usb2_id>;
@@ -417,28 +410,6 @@
};
};
- usb2_id: usb2-id {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_det_gpio>;
- };
-
- wlan_en: wlan-en-1-8v {
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_en_gpios>;
- compatible = "regulator-fixed";
- regulator-name = "wlan-en-regulator";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- gpio = <&pm8994_gpios 8 0>;
-
- /* WLAN card specific delay */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-
agnoc@0 {
pcie@600000 {
status = "okay";
@@ -667,6 +638,35 @@
};
};
};
+
+ usb2_id: usb2-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_gpio>;
+ };
+
+ usb3_id: usb3-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_det_gpio>;
+ };
+
+ wlan_en: wlan-en-1-8v {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_gpios>;
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8994_gpios 8 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
};
&spmi_bus {
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 02/11] arm64: dts: qcom: msm8996: Use node references in db820c
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
2019-10-21 5:13 ` [PATCH 01/11] arm64: dts: qcom: db820c: Move non-soc entries out of /soc Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 03/11] arm64: dts: qcom: msm8996: Move regulator consumers to db820c Bjorn Andersson
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Instead of mimicing the structure of the platform, reference nodes by
their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where
necessary.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 691 +++++++++----------
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +-
2 files changed, 341 insertions(+), 354 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index da2f01eb3be2..44ec3eb1c8e8 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -77,396 +77,383 @@
enable-gpios = <&pm8994_gpios 15 0>;
};
};
+};
- soc {
- serial@7570000 {
- label = "BT-UART";
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
+&blsp1_uart1 {
+ label = "BT-UART";
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart1_default>;
+ pinctrl-1 = <&blsp1_uart1_sleep>;
- bluetooth {
- compatible = "qcom,qca6174-bt";
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
- /* bt_disable_n gpio */
- enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ /* bt_disable_n gpio */
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
- clocks = <&divclk4>;
- };
- };
+ clocks = <&divclk4>;
+ };
+};
- serial@75b0000 {
- label = "LS-UART1";
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
- };
+&blsp2_uart1 {
+ label = "LS-UART1";
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart1_2pins_default>;
+ pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+};
- serial@75b1000 {
- label = "LS-UART0";
- status = "disabled";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart2_4pins_default>;
- pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
- };
+&blsp2_uart2 {
+ label = "LS-UART0";
+ status = "disabled";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_4pins_default>;
+ pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+};
- i2c@7577000 {
- /* On Low speed expansion */
- label = "LS-I2C0";
- status = "okay";
- };
+&blsp1_i2c2 {
+ /* On Low speed expansion */
+ label = "LS-I2C0";
+ status = "okay";
+};
- i2c@75b6000 {
- /* On Low speed expansion */
- label = "LS-I2C1";
- status = "okay";
- };
+&blsp2_i2c1 {
+ /* On Low speed expansion */
+ label = "LS-I2C1";
+ status = "okay";
+};
- spi@7575000 {
- /* On Low speed expansion */
- label = "LS-SPI0";
- status = "okay";
- };
+&blsp1_spi0 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
- i2c@75b5000 {
- /* On High speed expansion */
- label = "HS-I2C2";
- status = "okay";
- };
+&blsp2_i2c0 {
+ /* On High speed expansion */
+ label = "HS-I2C2";
+ status = "okay";
+};
- spi@75ba000{
- /* On High speed expansion */
- label = "HS-SPI1";
- status = "okay";
- };
+&blsp2_spi5 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
- sdhci@74a4900 {
- /* External SD card */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- cd-gpios = <&msmgpio 38 0x1>;
- vmmc-supply = <&pm8994_l21>;
- vqmmc-supply = <&pm8994_l13>;
- status = "okay";
- };
+&sdhc2 {
+ /* External SD card */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+ cd-gpios = <&msmgpio 38 0x1>;
+ vmmc-supply = <&pm8994_l21>;
+ vqmmc-supply = <&pm8994_l13>;
+ status = "okay";
+};
- phy@627000 {
- status = "okay";
- };
+&ufsphy {
+ status = "okay";
+};
- ufshc@624000 {
- status = "okay";
- };
+&ufshc {
+ status = "okay";
+};
- pinctrl@1010000 {
- gpio-line-names =
- "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
- "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
- "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
- "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
- "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
- "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
- "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
- "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
- "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
- "TP93", /* GPIO_9 */
- "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
- "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
- "NC", /* GPIO_12 */
- "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
- "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
- "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
- "TP99", /* GPIO_16 */
- "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
- "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
- "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
- "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
- "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
- "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
- "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
- "GPIO-D", /* GPIO_24, LSEC pin 26 */
- "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
- "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
- "BLSP6_I2C_SDA", /* GPIO_27 */
- "BLSP6_I2C_SCL", /* GPIO_28 */
- "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
- "GPIO30", /* GPIO_30, S HSEC pin 4 */
- "HDMI_CEC", /* GPIO_31 */
- "HDMI_DDC_CLOCK", /* GPIO_32 */
- "HDMI_DDC_DATA", /* GPIO_33 */
- "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
- "PCIE0_RST_N", /* GPIO_35 */
- "PCIE0_CLKREQ_N", /* GPIO_36 */
- "PCIE0_WAKE", /* GPIO_37 */
- "SD_CARD_DET_N", /* GPIO_38 */
- "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
- "W_DISABLE_N", /* GPIO_40 */
- "[BLSP9_UART_TX]", /* GPIO_41 */
- "[BLSP9_UART_RX]", /* GPIO_42 */
- "[BLSP2_UART_CTS_N]", /* GPIO_43 */
- "[BLSP2_UART_RFR_N]", /* GPIO_44 */
- "[BLSP3_UART_TX]", /* GPIO_45 */
- "[BLSP3_UART_RX]", /* GPIO_46 */
- "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
- "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
- "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
- "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
- "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
- "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
- "[CODEC_INT1_N]", /* GPIO_53 */
- "[CODEC_INT2_N]", /* GPIO_54 */
- "[BLSP7_I2C_SDA]", /* GPIO_55 */
- "[BLSP7_I2C_SCL]", /* GPIO_56 */
- "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
- "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
- "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
- "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
- "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
- "GPIO-E", /* GPIO_62, LSEC pin 27 */
- "TP87", /* GPIO_63 */
- "[CODEC_RST_N]", /* GPIO_64 */
- "[PCM1_CLK]", /* GPIO_65 */
- "[PCM1_SYNC]", /* GPIO_66 */
- "[PCM1_DIN]", /* GPIO_67 */
- "[PCM1_DOUT]", /* GPIO_68 */
- "AUDIO_REF_CLK", /* GPIO_69 */
- "SLIMBUS_CLK", /* GPIO_70 */
- "SLIMBUS_DATA0", /* GPIO_71 */
- "SLIMBUS_DATA1", /* GPIO_72 */
- "NC", /* GPIO_73 */
- "NC", /* GPIO_74 */
- "NC", /* GPIO_75 */
- "NC", /* GPIO_76 */
- "TP94", /* GPIO_77 */
- "NC", /* GPIO_78 */
- "TP95", /* GPIO_79 */
- "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
- "TP88", /* GPIO_81 */
- "TP89", /* GPIO_82 */
- "TP90", /* GPIO_83 */
- "TP91", /* GPIO_84 */
- "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
- "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
- "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
- "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
- "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
- "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
- "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
- "NC", /* GPIO_92 */
- "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
- "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
- "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
- "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
- "NC", /* GPIO_97 */
- "CAM1_STANDBY_N", /* GPIO_98 */
- "NC", /* GPIO_99 */
- "NC", /* GPIO_100 */
- "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
- "BOOT_CONFIG1", /* GPIO_102 */
- "USB_HUB_RESET", /* GPIO_103 */
- "CAM1_RST_N", /* GPIO_104 */
- "NC", /* GPIO_105 */
- "NC", /* GPIO_106 */
- "NC", /* GPIO_107 */
- "NC", /* GPIO_108 */
- "NC", /* GPIO_109 */
- "NC", /* GPIO_110 */
- "NC", /* GPIO_111 */
- "NC", /* GPIO_112 */
- "PMI8994_BUA", /* GPIO_113 */
- "PCIE2_RST_N", /* GPIO_114 */
- "PCIE2_CLKREQ_N", /* GPIO_115 */
- "PCIE2_WAKE", /* GPIO_116 */
- "SSC_IRQ_0", /* GPIO_117 */
- "SSC_IRQ_1", /* GPIO_118 */
- "SSC_IRQ_2", /* GPIO_119 */
- "NC", /* GPIO_120 */
- "GPIO121", /* GPIO_121, S HSEC pin 2 */
- "NC", /* GPIO_122 */
- "SSC_IRQ_6", /* GPIO_123 */
- "SSC_IRQ_7", /* GPIO_124 */
- "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
- "BOOT_CONFIG5", /* GPIO_126 */
- "NC", /* GPIO_127 */
- "NC", /* GPIO_128 */
- "BOOT_CONFIG7", /* GPIO_129 */
- "PCIE1_RST_N", /* GPIO_130 */
- "PCIE1_CLKREQ_N", /* GPIO_131 */
- "PCIE1_WAKE", /* GPIO_132 */
- "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
- "NC", /* GPIO_134 */
- "NC", /* GPIO_135 */
- "BOOT_CONFIG8", /* GPIO_136 */
- "NC", /* GPIO_137 */
- "NC", /* GPIO_138 */
- "GPS_SSBI2", /* GPIO_139 */
- "GPS_SSBI1", /* GPIO_140 */
- "NC", /* GPIO_141 */
- "NC", /* GPIO_142 */
- "NC", /* GPIO_143 */
- "BOOT_CONFIG6", /* GPIO_144 */
- "NC", /* GPIO_145 */
- "NC", /* GPIO_146 */
- "NC", /* GPIO_147 */
- "NC", /* GPIO_148 */
- "NC"; /* GPIO_149 */
- };
+&msmgpio {
+ gpio-line-names =
+ "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
+ "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
+ "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
+ "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
+ "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
+ "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
+ "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
+ "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
+ "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
+ "TP93", /* GPIO_9 */
+ "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
+ "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
+ "NC", /* GPIO_12 */
+ "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
+ "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
+ "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
+ "TP99", /* GPIO_16 */
+ "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
+ "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
+ "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
+ "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
+ "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
+ "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
+ "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
+ "GPIO-D", /* GPIO_24, LSEC pin 26 */
+ "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
+ "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
+ "BLSP6_I2C_SDA", /* GPIO_27 */
+ "BLSP6_I2C_SCL", /* GPIO_28 */
+ "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
+ "GPIO30", /* GPIO_30, S HSEC pin 4 */
+ "HDMI_CEC", /* GPIO_31 */
+ "HDMI_DDC_CLOCK", /* GPIO_32 */
+ "HDMI_DDC_DATA", /* GPIO_33 */
+ "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
+ "PCIE0_RST_N", /* GPIO_35 */
+ "PCIE0_CLKREQ_N", /* GPIO_36 */
+ "PCIE0_WAKE", /* GPIO_37 */
+ "SD_CARD_DET_N", /* GPIO_38 */
+ "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
+ "W_DISABLE_N", /* GPIO_40 */
+ "[BLSP9_UART_TX]", /* GPIO_41 */
+ "[BLSP9_UART_RX]", /* GPIO_42 */
+ "[BLSP2_UART_CTS_N]", /* GPIO_43 */
+ "[BLSP2_UART_RFR_N]", /* GPIO_44 */
+ "[BLSP3_UART_TX]", /* GPIO_45 */
+ "[BLSP3_UART_RX]", /* GPIO_46 */
+ "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
+ "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
+ "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
+ "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
+ "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
+ "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
+ "[CODEC_INT1_N]", /* GPIO_53 */
+ "[CODEC_INT2_N]", /* GPIO_54 */
+ "[BLSP7_I2C_SDA]", /* GPIO_55 */
+ "[BLSP7_I2C_SCL]", /* GPIO_56 */
+ "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
+ "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
+ "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
+ "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
+ "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
+ "GPIO-E", /* GPIO_62, LSEC pin 27 */
+ "TP87", /* GPIO_63 */
+ "[CODEC_RST_N]", /* GPIO_64 */
+ "[PCM1_CLK]", /* GPIO_65 */
+ "[PCM1_SYNC]", /* GPIO_66 */
+ "[PCM1_DIN]", /* GPIO_67 */
+ "[PCM1_DOUT]", /* GPIO_68 */
+ "AUDIO_REF_CLK", /* GPIO_69 */
+ "SLIMBUS_CLK", /* GPIO_70 */
+ "SLIMBUS_DATA0", /* GPIO_71 */
+ "SLIMBUS_DATA1", /* GPIO_72 */
+ "NC", /* GPIO_73 */
+ "NC", /* GPIO_74 */
+ "NC", /* GPIO_75 */
+ "NC", /* GPIO_76 */
+ "TP94", /* GPIO_77 */
+ "NC", /* GPIO_78 */
+ "TP95", /* GPIO_79 */
+ "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
+ "TP88", /* GPIO_81 */
+ "TP89", /* GPIO_82 */
+ "TP90", /* GPIO_83 */
+ "TP91", /* GPIO_84 */
+ "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
+ "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
+ "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
+ "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
+ "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
+ "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
+ "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
+ "NC", /* GPIO_92 */
+ "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
+ "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
+ "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
+ "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
+ "NC", /* GPIO_97 */
+ "CAM1_STANDBY_N", /* GPIO_98 */
+ "NC", /* GPIO_99 */
+ "NC", /* GPIO_100 */
+ "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
+ "BOOT_CONFIG1", /* GPIO_102 */
+ "USB_HUB_RESET", /* GPIO_103 */
+ "CAM1_RST_N", /* GPIO_104 */
+ "NC", /* GPIO_105 */
+ "NC", /* GPIO_106 */
+ "NC", /* GPIO_107 */
+ "NC", /* GPIO_108 */
+ "NC", /* GPIO_109 */
+ "NC", /* GPIO_110 */
+ "NC", /* GPIO_111 */
+ "NC", /* GPIO_112 */
+ "PMI8994_BUA", /* GPIO_113 */
+ "PCIE2_RST_N", /* GPIO_114 */
+ "PCIE2_CLKREQ_N", /* GPIO_115 */
+ "PCIE2_WAKE", /* GPIO_116 */
+ "SSC_IRQ_0", /* GPIO_117 */
+ "SSC_IRQ_1", /* GPIO_118 */
+ "SSC_IRQ_2", /* GPIO_119 */
+ "NC", /* GPIO_120 */
+ "GPIO121", /* GPIO_121, S HSEC pin 2 */
+ "NC", /* GPIO_122 */
+ "SSC_IRQ_6", /* GPIO_123 */
+ "SSC_IRQ_7", /* GPIO_124 */
+ "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
+ "BOOT_CONFIG5", /* GPIO_126 */
+ "NC", /* GPIO_127 */
+ "NC", /* GPIO_128 */
+ "BOOT_CONFIG7", /* GPIO_129 */
+ "PCIE1_RST_N", /* GPIO_130 */
+ "PCIE1_CLKREQ_N", /* GPIO_131 */
+ "PCIE1_WAKE", /* GPIO_132 */
+ "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
+ "NC", /* GPIO_134 */
+ "NC", /* GPIO_135 */
+ "BOOT_CONFIG8", /* GPIO_136 */
+ "NC", /* GPIO_137 */
+ "NC", /* GPIO_138 */
+ "GPS_SSBI2", /* GPIO_139 */
+ "GPS_SSBI1", /* GPIO_140 */
+ "NC", /* GPIO_141 */
+ "NC", /* GPIO_142 */
+ "NC", /* GPIO_143 */
+ "BOOT_CONFIG6", /* GPIO_144 */
+ "NC", /* GPIO_145 */
+ "NC", /* GPIO_146 */
+ "NC", /* GPIO_147 */
+ "NC", /* GPIO_148 */
+ "NC"; /* GPIO_149 */
+};
- qcom,spmi@400f000 {
- pmic@0 {
- gpios@c000 {
- gpio-line-names =
- "NC",
- "KEY_VOLP_N",
- "NC",
- "BL1_PWM",
- "GPIO-F", /* BL0_PWM, LSEC pin 28 */
- "BL1_EN",
- "NC",
- "WLAN_EN",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC",
- "NC",
- "DIVCLK1",
- "DIVCLK2",
- "DIVCLK3",
- "DIVCLK4",
- "BT_EN",
- "PMIC_SLB",
- "PMIC_BUA",
- "USB_VBUS_DET";
- };
-
- mpps@a000 {
- gpio-line-names =
- "VDDPX_BIAS",
- "WIFI_LED",
- "NC",
- "BT_LED",
- "PM_MPP05",
- "PM_MPP06",
- "PM_MPP07",
- "NC";
- };
- };
+&pm8994_gpios {
+ gpio-line-names =
+ "NC",
+ "KEY_VOLP_N",
+ "NC",
+ "BL1_PWM",
+ "GPIO-F", /* BL0_PWM, LSEC pin 28 */
+ "BL1_EN",
+ "NC",
+ "WLAN_EN",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "DIVCLK1",
+ "DIVCLK2",
+ "DIVCLK3",
+ "DIVCLK4",
+ "BT_EN",
+ "PMIC_SLB",
+ "PMIC_BUA",
+ "USB_VBUS_DET";
+};
- pmic@2 {
- gpios@c000 {
- gpio-line-names =
- "NC",
- "SPKR_AMP_EN1",
- "SPKR_AMP_EN2",
- "TP61",
- "NC",
- "USB2_VBUS_DET",
- "NC",
- "NC",
- "NC",
- "NC";
- };
- };
- };
+&pm8994_mpps {
+ gpio-line-names =
+ "VDDPX_BIAS",
+ "WIFI_LED",
+ "NC",
+ "BT_LED",
+ "PM_MPP05",
+ "PM_MPP06",
+ "PM_MPP07",
+ "NC";
+};
- phy@34000 {
- status = "okay";
- };
+&pmi8994_gpios {
+ gpio-line-names =
+ "NC",
+ "SPKR_AMP_EN1",
+ "SPKR_AMP_EN2",
+ "TP61",
+ "NC",
+ "USB2_VBUS_DET",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
- phy@7410000 {
- status = "okay";
- };
+&pcie_phy {
+ status = "okay";
+};
- phy@7411000 {
- status = "okay";
- };
+&usb3phy {
+ status = "okay";
+};
- phy@7412000 {
- status = "okay";
- };
+&hsusb_phy1 {
+ status = "okay";
+};
- usb@6af8800 {
- status = "okay";
- extcon = <&usb3_id>;
+&hsusb_phy2 {
+ status = "okay";
+};
- dwc3@6a00000 {
- extcon = <&usb3_id>;
- dr_mode = "otg";
- };
- };
+&usb3 {
+ status = "okay";
+ extcon = <&usb3_id>;
- usb@76f8800 {
- status = "okay";
- extcon = <&usb2_id>;
+ dwc3@6a00000 {
+ extcon = <&usb3_id>;
+ dr_mode = "otg";
+ };
+};
- dwc3@7600000 {
- extcon = <&usb2_id>;
- dr_mode = "otg";
- maximum-speed = "high-speed";
- };
- };
+&usb2 {
+ status = "okay";
+ extcon = <&usb2_id>;
- agnoc@0 {
- pcie@600000 {
- status = "okay";
- perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
- vddpe-3v3-supply = <&wlan_en>;
- };
+ dwc3@7600000 {
+ extcon = <&usb2_id>;
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ };
+};
- pcie@608000 {
- status = "okay";
- perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
- };
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&wlan_en>;
+};
- pcie@610000 {
- status = "okay";
- perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
- };
- };
+&pcie1 {
+ status = "okay";
+ perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+};
- slim_msm: slim@91c0000 {
- ngd@1 {
- wcd9335: codec@1{
- clock-names = "mclk", "slimbus";
- clocks = <&div1_mclk>,
- <&rpmcc RPM_SMD_BB_CLK1>;
- };
- };
- };
+&pcie2 {
+ status = "okay";
+ perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+};
- mdss@900000 {
- status = "okay";
+&wcd9335 {
+ clock-names = "mclk", "slimbus";
+ clocks = <&div1_mclk>,
+ <&rpmcc RPM_SMD_BB_CLK1>;
+};
- mdp@901000 {
- status = "okay";
- };
+&mdss {
+ status = "okay";
+};
- hdmi-phy@9a0600 {
- status = "okay";
+&mdp {
+ status = "okay";
+};
- vddio-supply = <&pm8994_l12>;
- vcca-supply = <&pm8994_l28>;
- #phy-cells = <0>;
- };
+&hdmi_phy {
+ status = "okay";
- hdmi-tx@9a0000 {
- status = "okay";
+ vddio-supply = <&pm8994_l12>;
+ vcca-supply = <&pm8994_l28>;
+ #phy-cells = <0>;
+};
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
- pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+&hdmi {
+ status = "okay";
- core-vdda-supply = <&pm8994_l12>;
- core-vcc-supply = <&pm8994_s4>;
- };
- };
- };
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+ pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+ core-vdda-supply = <&pm8994_l12>;
+ core-vcc-supply = <&pm8994_s4>;
+};
+/ {
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 87f4d9c1b0d4..36f161547aa6 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1443,7 +1443,7 @@
};
};
- phy@34000 {
+ pcie_phy: phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x34000 0x488>;
#clock-cells = <1>;
@@ -1505,7 +1505,7 @@
};
};
- phy@7410000 {
+ usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x7410000 0x1c4>;
#clock-cells = <1>;
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 03/11] arm64: dts: qcom: msm8996: Move regulator consumers to db820c
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
2019-10-21 5:13 ` [PATCH 01/11] arm64: dts: qcom: db820c: Move non-soc entries out of /soc Bjorn Andersson
2019-10-21 5:13 ` [PATCH 02/11] arm64: dts: qcom: msm8996: Use node references in db820c Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 04/11] arm64: dts: qcom: msm8996: Move regulators " Bjorn Andersson
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Supplies for the various components in the SoC depends on board layout,
so move the supply definitions to db820c.dtsi instead of carrying them
in the platform dtsi.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 44 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 44 --------------------
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 44ec3eb1c8e8..21e029afb27b 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -142,6 +142,10 @@
status = "okay";
};
+&camss {
+ vdda-supply = <&pm8994_l2>;
+};
+
&sdhc2 {
/* External SD card */
pinctrl-names = "default", "sleep";
@@ -155,10 +159,28 @@
&ufsphy {
status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ vdda-phy-max-microamp = <18380>;
+ vdda-pll-max-microamp = <9440>;
+
+ vddp-ref-clk-supply = <&pm8994_l25>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
};
&ufshc {
status = "okay";
+
+ vcc-supply = <&pm8994_l20>;
+ vccq-supply = <&pm8994_l25>;
+ vccq2-supply = <&pm8994_s4>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
};
&msmgpio {
@@ -369,18 +391,31 @@
&pcie_phy {
status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
};
&usb3phy {
status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
};
&hsusb_phy1 {
status = "okay";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
};
&hsusb_phy2 {
status = "okay";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
};
&usb3 {
@@ -408,22 +443,31 @@
status = "okay";
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
+ vdda-supply = <&pm8994_l28>;
};
&pcie1 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&pm8994_l28>;
};
&pcie2 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&pm8994_l28>;
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
+
+ vdd-buck-supply = <&pm8994_s4>;
+ vdd-buck-sido-supply = <&pm8994_s4>;
+ vdd-tx-supply = <&pm8994_s4>;
+ vdd-rx-supply = <&pm8994_s4>;
+ vdd-io-supply = <&pm8994_s4>;
};
&mdss {
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 36f161547aa6..a297d3223161 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1322,16 +1322,6 @@
reg-names = "phy_mem";
#phy-cells = <0>;
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
- vdda-phy-max-microamp = <18380>;
- vdda-pll-max-microamp = <9440>;
-
- vddp-ref-clk-supply = <&pm8994_l25>;
- vddp-ref-clk-max-microamp = <100>;
- vddp-ref-clk-always-on;
-
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
@@ -1347,14 +1337,6 @@
phys = <&ufsphy>;
phy-names = "ufsphy";
- vcc-supply = <&pm8994_l20>;
- vccq-supply = <&pm8994_l25>;
- vccq2-supply = <&pm8994_s4>;
-
- vcc-max-microamp = <600000>;
- vccq-max-microamp = <450000>;
- vccq2-max-microamp = <450000>;
-
power-domains = <&gcc UFS_GDSC>;
clock-names =
@@ -1456,9 +1438,6 @@
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
@@ -1518,9 +1497,6 @@
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
@@ -1547,9 +1523,6 @@
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
-
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
status = "disabled";
@@ -1564,9 +1537,6 @@
<&gcc GCC_RX2_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
-
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
@@ -1770,7 +1740,6 @@
"vfe1_stream",
"vfe_ahb",
"vfe_axi";
- vdda-supply = <&pm8994_l2>;
iommus = <&vfe_smmu 0>,
<&vfe_smmu 1>,
<&vfe_smmu 2>,
@@ -1882,9 +1851,6 @@
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
-
- vdda-supply = <&pm8994_l28>;
-
linux,pci-domain = <0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
@@ -1937,8 +1903,6 @@
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
-
- vdda-supply = <&pm8994_l28>;
linux,pci-domain = <1>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
@@ -1990,8 +1954,6 @@
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
- vdda-supply = <&pm8994_l28>;
-
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
@@ -2056,12 +2018,6 @@
slim-ifc-dev = <&tasha_ifd>;
- vdd-buck-supply = <&pm8994_s4>;
- vdd-buck-sido-supply = <&pm8994_s4>;
- vdd-tx-supply = <&pm8994_s4>;
- vdd-rx-supply = <&pm8994_s4>;
- vdd-io-supply = <&pm8994_s4>;
-
#sound-dai-cells = <1>;
};
};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 04/11] arm64: dts: qcom: msm8996: Move regulators to db820c
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (2 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 03/11] arm64: dts: qcom: msm8996: Move regulator consumers to db820c Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 05/11] arm64: dts: qcom: db820c: Group root nodes Bjorn Andersson
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
As the definition of available PMICs and the names of their outputs are
board specifc move this to db820c.dtsi
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 308 ++++++++++---------
arch/arm64/boot/dts/qcom/msm8996.dtsi | 53 +---
2 files changed, 156 insertions(+), 205 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 21e029afb27b..fc6273b0215d 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -513,163 +513,165 @@
gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
};
};
+};
- rpm-glink {
- rpm_requests {
- pm8994-regulators {
- vdd_l1-supply = <&pm8994_s3>;
- vdd_l2_l26_l28-supply = <&pm8994_s3>;
- vdd_l3_l11-supply = <&pm8994_s3>;
- vdd_l4_l27_l31-supply = <&pm8994_s3>;
- vdd_l5_l7-supply = <&pm8994_s5>;
- vdd_l14_l15-supply = <&pm8994_s5>;
- vdd_l20_l21-supply = <&pm8994_s5>;
- vdd_l25-supply = <&pm8994_s3>;
-
- s3 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- };
-
- /**
- * 1.8v required on LS expansion
- * for mezzanine boards
- */
- s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
- s5 {
- regulator-min-microvolt = <2150000>;
- regulator-max-microvolt = <2150000>;
- };
- s7 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- };
-
- l1 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
- l2 {
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- };
- l3 {
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- };
- l4 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1225000>;
- };
- l6 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
- l8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l10 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l11 {
- regulator-min-microvolt = <1150000>;
- regulator-max-microvolt = <1150000>;
- };
- l12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l13 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2950000>;
- };
- l14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l15 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l16 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2700000>;
- };
- l17 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- };
- l18 {
- regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <2900000>;
- };
- l19 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
- l20 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- regulator-allow-set-load;
- };
- l21 {
- regulator-min-microvolt = <2950000>;
- regulator-max-microvolt = <2950000>;
- regulator-allow-set-load;
- regulator-system-load = <200000>;
- };
- l22 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
- l23 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
- l24 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3075000>;
- };
- l25 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-allow-set-load;
- };
- l27 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
- l28 {
- regulator-min-microvolt = <925000>;
- regulator-max-microvolt = <925000>;
- regulator-allow-set-load;
- };
- l29 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
- l30 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- l32 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- };
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_l1-supply = <&pm8994_s3>;
+ vdd_l2_l26_l28-supply = <&pm8994_s3>;
+ vdd_l3_l11-supply = <&pm8994_s3>;
+ vdd_l4_l27_l31-supply = <&pm8994_s3>;
+ vdd_l5_l7-supply = <&pm8994_s5>;
+ vdd_l14_l15-supply = <&pm8994_s5>;
+ vdd_l20_l21-supply = <&pm8994_s5>;
+ vdd_l25-supply = <&pm8994_s3>;
+
+ pm8994_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ /**
+ * 1.8v required on LS expansion
+ * for mezzanine boards
+ */
+ pm8994_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ pm8994_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+ pm8994_s7: s7 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ pm8994_l1: l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ pm8994_l2: l2 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+ pm8994_l3: l3 {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ };
+ pm8994_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ pm8994_l6: l6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ pm8994_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l11: l11 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+ pm8994_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ pm8994_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ pm8994_l17: l17 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+ pm8994_l18: l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+ pm8994_l19: l19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ pm8994_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+ pm8994_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+ pm8994_l22: l22 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ pm8994_l23: l23 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ pm8994_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ pm8994_l25: l25 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+ pm8994_l27: l27 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ pm8994_l28: l28 {
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-allow-set-load;
+ };
+ pm8994_l29: l29 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ pm8994_l30: l30 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ pm8994_l32: l32 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
};
+};
+/ {
usb2_id: usb2-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index a297d3223161..48b5981d01b0 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -467,7 +467,7 @@
mboxes = <&apcs_glb 0>;
- rpm_requests {
+ rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
@@ -509,57 +509,6 @@
};
};
};
-
- pm8994-regulators {
- compatible = "qcom,rpm-pm8994-regulators";
-
- pm8994_s1: s1 {};
- pm8994_s2: s2 {};
- pm8994_s3: s3 {};
- pm8994_s4: s4 {};
- pm8994_s5: s5 {};
- pm8994_s6: s6 {};
- pm8994_s7: s7 {};
- pm8994_s8: s8 {};
- pm8994_s9: s9 {};
- pm8994_s10: s10 {};
- pm8994_s11: s11 {};
- pm8994_s12: s12 {};
-
- pm8994_l1: l1 {};
- pm8994_l2: l2 {};
- pm8994_l3: l3 {};
- pm8994_l4: l4 {};
- pm8994_l5: l5 {};
- pm8994_l6: l6 {};
- pm8994_l7: l7 {};
- pm8994_l8: l8 {};
- pm8994_l9: l9 {};
- pm8994_l10: l10 {};
- pm8994_l11: l11 {};
- pm8994_l12: l12 {};
- pm8994_l13: l13 {};
- pm8994_l14: l14 {};
- pm8994_l15: l15 {};
- pm8994_l16: l16 {};
- pm8994_l17: l17 {};
- pm8994_l18: l18 {};
- pm8994_l19: l19 {};
- pm8994_l20: l20 {};
- pm8994_l21: l21 {};
- pm8994_l22: l22 {};
- pm8994_l23: l23 {};
- pm8994_l24: l24 {};
- pm8994_l25: l25 {};
- pm8994_l26: l26 {};
- pm8994_l27: l27 {};
- pm8994_l28: l28 {};
- pm8994_l29: l29 {};
- pm8994_l30: l30 {};
- pm8994_l31: l31 {};
- pm8994_l32: l32 {};
- };
-
};
};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 05/11] arm64: dts: qcom: db820c: Group root nodes
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (3 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 04/11] arm64: dts: qcom: msm8996: Move regulators " Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 06/11] arm64: dts: qcom: db820c: Sort all nodes Bjorn Andersson
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Prior refactoring have left a few root nodes scattered throughout
db820c.dtsi, group these at the top of the file.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 94 ++++++++++----------
1 file changed, 45 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index fc6273b0215d..aed34a461b19 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -77,6 +77,51 @@
enable-gpios = <&pm8994_gpios 15 0>;
};
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&volume_up_gpio>;
+
+ button@0 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usb2_id: usb2-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_gpio>;
+ };
+
+ usb3_id: usb3-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_det_gpio>;
+ };
+
+ wlan_en: wlan-en-1-8v {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_gpios>;
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8994_gpios 8 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
};
&blsp1_uart1 {
@@ -497,24 +542,6 @@
core-vcc-supply = <&pm8994_s4>;
};
-/ {
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- autorepeat;
-
- pinctrl-names = "default";
- pinctrl-0 = <&volume_up_gpio>;
-
- button@0 {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@@ -671,37 +698,6 @@
};
};
-/ {
- usb2_id: usb2-id {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_det_gpio>;
- };
-
- usb3_id: usb3-id {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&usb3_vbus_det_gpio>;
- };
-
- wlan_en: wlan-en-1-8v {
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_en_gpios>;
- compatible = "regulator-fixed";
- regulator-name = "wlan-en-regulator";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- gpio = <&pm8994_gpios 8 0>;
-
- /* WLAN card specific delay */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-};
-
&spmi_bus {
pmic@0 {
pon@800 {
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 06/11] arm64: dts: qcom: db820c: Sort all nodes
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (4 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 05/11] arm64: dts: qcom: db820c: Group root nodes Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 07/11] arm64: dts: qcom: db820c: Remove pin specific files Bjorn Andersson
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Sort all nodes in db820c.dtsi based on address, then name.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 336 +++++++++----------
1 file changed, 168 insertions(+), 168 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index aed34a461b19..99990a139938 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -124,6 +124,18 @@
};
};
+&blsp1_i2c2 {
+ /* On Low speed expansion */
+ label = "LS-I2C0";
+ status = "okay";
+};
+
+&blsp1_spi0 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
&blsp1_uart1 {
label = "BT-UART";
status = "okay";
@@ -141,6 +153,24 @@
};
};
+&blsp2_i2c0 {
+ /* On High speed expansion */
+ label = "HS-I2C2";
+ status = "okay";
+};
+
+&blsp2_i2c1 {
+ /* On Low speed expansion */
+ label = "LS-I2C1";
+ status = "okay";
+};
+
+&blsp2_spi5 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
+
&blsp2_uart1 {
label = "LS-UART1";
status = "okay";
@@ -157,75 +187,49 @@
pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
};
-&blsp1_i2c2 {
- /* On Low speed expansion */
- label = "LS-I2C0";
- status = "okay";
+&camss {
+ vdda-supply = <&pm8994_l2>;
};
-&blsp2_i2c1 {
- /* On Low speed expansion */
- label = "LS-I2C1";
+&hdmi {
status = "okay";
-};
-&blsp1_spi0 {
- /* On Low speed expansion */
- label = "LS-SPI0";
- status = "okay";
-};
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+ pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
-&blsp2_i2c0 {
- /* On High speed expansion */
- label = "HS-I2C2";
- status = "okay";
+ core-vdda-supply = <&pm8994_l12>;
+ core-vcc-supply = <&pm8994_s4>;
};
-&blsp2_spi5 {
- /* On High speed expansion */
- label = "HS-SPI1";
+&hdmi_phy {
status = "okay";
-};
-&camss {
- vdda-supply = <&pm8994_l2>;
+ vddio-supply = <&pm8994_l12>;
+ vcca-supply = <&pm8994_l28>;
+ #phy-cells = <0>;
};
-&sdhc2 {
- /* External SD card */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- cd-gpios = <&msmgpio 38 0x1>;
- vmmc-supply = <&pm8994_l21>;
- vqmmc-supply = <&pm8994_l13>;
+&hsusb_phy1 {
status = "okay";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
};
-&ufsphy {
+&hsusb_phy2 {
status = "okay";
- vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
-
- vdda-phy-max-microamp = <18380>;
- vdda-pll-max-microamp = <9440>;
-
- vddp-ref-clk-supply = <&pm8994_l25>;
- vddp-ref-clk-max-microamp = <100>;
- vddp-ref-clk-always-on;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
};
-&ufshc {
+&mdp {
status = "okay";
+};
- vcc-supply = <&pm8994_l20>;
- vccq-supply = <&pm8994_l25>;
- vccq2-supply = <&pm8994_s4>;
-
- vcc-max-microamp = <600000>;
- vccq-max-microamp = <450000>;
- vccq2-max-microamp = <450000>;
+&mdss {
+ status = "okay";
};
&msmgpio {
@@ -382,6 +386,32 @@
"NC"; /* GPIO_149 */
};
+&pcie0 {
+ status = "okay";
+ perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&wlan_en>;
+ vdda-supply = <&pm8994_l28>;
+};
+
+&pcie1 {
+ status = "okay";
+ perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&pm8994_l28>;
+};
+
+&pcie2 {
+ status = "okay";
+ perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&pm8994_l28>;
+};
+
+&pcie_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+};
+
&pm8994_gpios {
gpio-line-names =
"NC",
@@ -434,114 +464,6 @@
"NC";
};
-&pcie_phy {
- status = "okay";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-};
-
-&usb3phy {
- status = "okay";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
-};
-
-&hsusb_phy1 {
- status = "okay";
-
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
-};
-
-&hsusb_phy2 {
- status = "okay";
-
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
-};
-
-&usb3 {
- status = "okay";
- extcon = <&usb3_id>;
-
- dwc3@6a00000 {
- extcon = <&usb3_id>;
- dr_mode = "otg";
- };
-};
-
-&usb2 {
- status = "okay";
- extcon = <&usb2_id>;
-
- dwc3@7600000 {
- extcon = <&usb2_id>;
- dr_mode = "otg";
- maximum-speed = "high-speed";
- };
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
- vddpe-3v3-supply = <&wlan_en>;
- vdda-supply = <&pm8994_l28>;
-};
-
-&pcie1 {
- status = "okay";
- perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
- vdda-supply = <&pm8994_l28>;
-};
-
-&pcie2 {
- status = "okay";
- perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
- vdda-supply = <&pm8994_l28>;
-};
-
-&wcd9335 {
- clock-names = "mclk", "slimbus";
- clocks = <&div1_mclk>,
- <&rpmcc RPM_SMD_BB_CLK1>;
-
- vdd-buck-supply = <&pm8994_s4>;
- vdd-buck-sido-supply = <&pm8994_s4>;
- vdd-tx-supply = <&pm8994_s4>;
- vdd-rx-supply = <&pm8994_s4>;
- vdd-io-supply = <&pm8994_s4>;
-};
-
-&mdss {
- status = "okay";
-};
-
-&mdp {
- status = "okay";
-};
-
-&hdmi_phy {
- status = "okay";
-
- vddio-supply = <&pm8994_l12>;
- vcca-supply = <&pm8994_l28>;
- #phy-cells = <0>;
-};
-
-&hdmi {
- status = "okay";
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
- pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
-
- core-vdda-supply = <&pm8994_l12>;
- core-vcc-supply = <&pm8994_s4>;
-};
-
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@@ -698,18 +620,15 @@
};
};
-&spmi_bus {
- pmic@0 {
- pon@800 {
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
- };
- };
+&sdhc2 {
+ /* External SD card */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+ cd-gpios = <&msmgpio 38 0x1>;
+ vmmc-supply = <&pm8994_l21>;
+ vqmmc-supply = <&pm8994_l13>;
+ status = "okay";
};
&sound {
@@ -783,3 +702,84 @@
};
};
};
+
+&spmi_bus {
+ pmic@0 {
+ pon@800 {
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+ };
+};
+
+&ufsphy {
+ status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ vdda-phy-max-microamp = <18380>;
+ vdda-pll-max-microamp = <9440>;
+
+ vddp-ref-clk-supply = <&pm8994_l25>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+};
+
+&ufshc {
+ status = "okay";
+
+ vcc-supply = <&pm8994_l20>;
+ vccq-supply = <&pm8994_l25>;
+ vccq2-supply = <&pm8994_s4>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
+};
+
+&usb2 {
+ status = "okay";
+ extcon = <&usb2_id>;
+
+ dwc3@7600000 {
+ extcon = <&usb2_id>;
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ };
+};
+
+&usb3 {
+ status = "okay";
+ extcon = <&usb3_id>;
+
+ dwc3@6a00000 {
+ extcon = <&usb3_id>;
+ dr_mode = "otg";
+ };
+};
+
+&usb3phy {
+ status = "okay";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+};
+
+&wcd9335 {
+ clock-names = "mclk", "slimbus";
+ clocks = <&div1_mclk>,
+ <&rpmcc RPM_SMD_BB_CLK1>;
+
+ vdd-buck-supply = <&pm8994_s4>;
+ vdd-buck-sido-supply = <&pm8994_s4>;
+ vdd-tx-supply = <&pm8994_s4>;
+ vdd-rx-supply = <&pm8994_s4>;
+ vdd-io-supply = <&pm8994_s4>;
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 07/11] arm64: dts: qcom: db820c: Remove pin specific files
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (5 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 06/11] arm64: dts: qcom: db820c: Sort all nodes Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 08/11] arm64: dts: qcom: msm8996: Pad addresses Bjorn Andersson
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Rather than scattering pinctrl definitions in various files, merge the
nodes into db820c.dtsi to make it easier to navigate.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
.../boot/dts/qcom/apq8096-db820c-pins.dtsi | 109 ----------
.../dts/qcom/apq8096-db820c-pmic-pins.dtsi | 92 ---------
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 192 +++++++++++++++++-
3 files changed, 190 insertions(+), 203 deletions(-)
delete mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
delete mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
deleted file mode 100644
index a5cc80d6e82f..000000000000
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
- */
-&msmgpio {
- sdc2_cd_on: sdc2_cd_on {
- mux {
- pins = "gpio38";
- function = "gpio";
- };
-
- config {
- pins = "gpio38";
- bias-pull-up; /* pull up */
- drive-strength = <16>; /* 16 MA */
- };
- };
-
- sdc2_cd_off: sdc2_cd_off {
- mux {
- pins = "gpio38";
- function = "gpio";
- };
-
- config {
- pins = "gpio38";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- blsp1_uart1_default: blsp1_uart1_default {
- mux {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- function = "blsp_uart2";
- };
-
- config {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp1_uart1_sleep: blsp1_uart1_sleep {
- mux {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- function = "gpio";
- };
-
- config {
- pins = "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- hdmi_hpd_active: hdmi_hpd_active {
- mux {
- pins = "gpio34";
- function = "hdmi_hot";
- };
-
- config {
- pins = "gpio34";
- bias-pull-down;
- drive-strength = <16>;
- };
- };
-
- hdmi_hpd_suspend: hdmi_hpd_suspend {
- mux {
- pins = "gpio34";
- function = "hdmi_hot";
- };
-
- config {
- pins = "gpio34";
- bias-pull-down;
- drive-strength = <2>;
- };
- };
-
- hdmi_ddc_active: hdmi_ddc_active {
- mux {
- pins = "gpio32", "gpio33";
- function = "hdmi_ddc";
- };
-
- config {
- pins = "gpio32", "gpio33";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- hdmi_ddc_suspend: hdmi_ddc_suspend {
- mux {
- pins = "gpio32", "gpio33";
- function = "hdmi_ddc";
- };
-
- config {
- pins = "gpio32", "gpio33";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
deleted file mode 100644
index 31a3e3311ad5..000000000000
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-&pm8994_gpios {
-
- pinctrl-names = "default";
- pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
-
- ls_exp_gpio_f: pm8994_gpio5 {
- pinconf {
- pins = "gpio5";
- output-low;
- power-source = <2>; // PM8994_GPIO_S4, 1.8V
- };
- };
-
- bt_en_gpios: bt_en_gpios {
- pinconf {
- pins = "gpio19";
- function = PMIC_GPIO_FUNC_NORMAL;
- output-low;
- power-source = <PM8994_GPIO_S4>; // 1.8V
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
- bias-pull-down;
- };
- };
-
- wlan_en_gpios: wlan_en_gpios {
- pinconf {
- pins = "gpio8";
- function = PMIC_GPIO_FUNC_NORMAL;
- output-low;
- power-source = <PM8994_GPIO_S4>; // 1.8V
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
- bias-pull-down;
- };
- };
-
- audio_mclk: clk_div1 {
- pinconf {
- pins = "gpio15";
- function = "func1";
- power-source = <PM8994_GPIO_S4>; // 1.8V
- };
- };
-
- volume_up_gpio: pm8996_gpio2 {
- pinconf {
- pins = "gpio2";
- function = "normal";
- input-enable;
- drive-push-pull;
- bias-pull-up;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
- };
- };
-
- divclk4_pin_a: divclk4 {
- pinconf {
- pins = "gpio18";
- function = PMIC_GPIO_FUNC_FUNC2;
-
- bias-disable;
- power-source = <PM8994_GPIO_S4>;
- };
- };
-
- usb3_vbus_det_gpio: pm8996_gpio22 {
- pinconf {
- pins = "gpio22";
- function = PMIC_GPIO_FUNC_NORMAL;
- input-enable;
- bias-pull-down;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
- };
- };
-};
-
-&pmi8994_gpios {
- usb2_vbus_det_gpio: pmi8996_gpio6 {
- pinconf {
- pins = "gpio6";
- function = PMIC_GPIO_FUNC_NORMAL;
- input-enable;
- bias-pull-down;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
- };
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 99990a139938..6c64deecf950 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -6,10 +6,9 @@
#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
-#include "apq8096-db820c-pins.dtsi"
-#include "apq8096-db820c-pmic-pins.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -384,6 +383,110 @@
"NC", /* GPIO_147 */
"NC", /* GPIO_148 */
"NC"; /* GPIO_149 */
+
+ sdc2_cd_on: sdc2_cd_on {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cd_off: sdc2_cd_off {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ blsp1_uart1_default: blsp1_uart1_default {
+ mux {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart1_sleep: blsp1_uart1_sleep {
+ mux {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ hdmi_hpd_active: hdmi_hpd_active {
+ mux {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ hdmi_hpd_suspend: hdmi_hpd_suspend {
+ mux {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ hdmi_ddc_active: hdmi_ddc_active {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hdmi_ddc_suspend: hdmi_ddc_suspend {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
};
&pcie0 {
@@ -436,6 +539,80 @@
"PMIC_SLB",
"PMIC_BUA",
"USB_VBUS_DET";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
+
+ ls_exp_gpio_f: pm8994_gpio5 {
+ pinconf {
+ pins = "gpio5";
+ output-low;
+ power-source = <2>; // PM8994_GPIO_S4, 1.8V
+ };
+ };
+
+ bt_en_gpios: bt_en_gpios {
+ pinconf {
+ pins = "gpio19";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ bias-pull-down;
+ };
+ };
+
+ wlan_en_gpios: wlan_en_gpios {
+ pinconf {
+ pins = "gpio8";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ bias-pull-down;
+ };
+ };
+
+ audio_mclk: clk_div1 {
+ pinconf {
+ pins = "gpio15";
+ function = "func1";
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
+
+ volume_up_gpio: pm8996_gpio2 {
+ pinconf {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ drive-push-pull;
+ bias-pull-up;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
+
+ divclk4_pin_a: divclk4 {
+ pinconf {
+ pins = "gpio18";
+ function = PMIC_GPIO_FUNC_FUNC2;
+
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ };
+ };
+
+ usb3_vbus_det_gpio: pm8996_gpio22 {
+ pinconf {
+ pins = "gpio22";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
};
&pm8994_mpps {
@@ -462,6 +639,17 @@
"NC",
"NC",
"NC";
+
+ usb2_vbus_det_gpio: pmi8996_gpio6 {
+ pinconf {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
};
&rpm_requests {
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 08/11] arm64: dts: qcom: msm8996: Pad addresses
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (6 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 07/11] arm64: dts: qcom: db820c: Remove pin specific files Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 09/11] arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi Bjorn Andersson
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it
easier to ensure ordering when adding new nodes.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 144 +++++++++++++-------------
1 file changed, 72 insertions(+), 72 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 48b5981d01b0..6c1a6774396d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -520,7 +520,7 @@
rpm_msg_ram: memory@68000 {
compatible = "qcom,rpm-msg-ram";
- reg = <0x68000 0x6000>;
+ reg = <0x00068000 0x6000>;
};
rng: rng@83000 {
@@ -532,28 +532,28 @@
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
- reg = <0x740000 0x20000>;
+ reg = <0x00740000 0x20000>;
};
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens";
- reg = <0x4a9000 0x1000>, /* TM */
- <0x4a8000 0x1000>; /* SROT */
+ reg = <0x004a9000 0x1000>, /* TM */
+ <0x004a8000 0x1000>; /* SROT */
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens";
- reg = <0x4ad000 0x1000>, /* TM */
- <0x4ac000 0x1000>; /* SROT */
+ reg = <0x004ad000 0x1000>, /* TM */
+ <0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
- reg = <0x7a0000 0x18000>;
+ reg = <0x007a0000 0x18000>;
};
intc: interrupt-controller@9bc0000 {
@@ -569,7 +569,7 @@
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
- reg = <0x9820000 0x1000>;
+ reg = <0x09820000 0x1000>;
#mbox-cells = <1>;
};
@@ -579,7 +579,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- reg = <0x300000 0x90000>;
+ reg = <0x00300000 0x90000>;
};
stm@3002000 {
@@ -1052,7 +1052,7 @@
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
- reg = <0x6400000 0x90000>;
+ reg = <0x06400000 0x90000>;
#clock-cells = <1>;
};
@@ -1098,7 +1098,7 @@
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x75b0000 0x1000>;
+ reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
@@ -1164,7 +1164,7 @@
sdhc2: sdhci@74a4900 {
status = "disabled";
compatible = "qcom,sdhci-msm-v4";
- reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
@@ -1249,11 +1249,11 @@
spmi_bus: qcom,spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0x400f000 0x1000>,
- <0x4400000 0x800000>,
- <0x4c00000 0x800000>,
- <0x5800000 0x200000>,
- <0x400a000 0x002100>;
+ reg = <0x0400f000 0x1000>,
+ <0x04400000 0x800000>,
+ <0x04c00000 0x800000>,
+ <0x05800000 0x200000>,
+ <0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
@@ -1267,7 +1267,7 @@
ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
- reg = <0x627000 0xda8>;
+ reg = <0x00627000 0xda8>;
reg-names = "phy_mem";
#phy-cells = <0>;
@@ -1280,7 +1280,7 @@
ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
- reg = <0x624000 0x2500>;
+ reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy>;
@@ -1339,7 +1339,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- reg = <0x8c0000 0x40000>;
+ reg = <0x008c0000 0x40000>;
assigned-clocks = <&mmcc MMPLL9_PLL>,
<&mmcc MMPLL1_PLL>,
<&mmcc MMPLL3_PLL>,
@@ -1354,7 +1354,7 @@
qfprom@74000 {
compatible = "qcom,qfprom";
- reg = <0x74000 0x8ff>;
+ reg = <0x00074000 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1376,7 +1376,7 @@
pcie_phy: phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x34000 0x488>;
+ reg = <0x00034000 0x488>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1394,9 +1394,9 @@
status = "disabled";
pciephy_0: lane@35000 {
- reg = <0x035000 0x130>,
- <0x035200 0x200>,
- <0x035400 0x1dc>;
+ reg = <0x00035000 0x130>,
+ <0x00035200 0x200>,
+ <0x00035400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
@@ -1407,9 +1407,9 @@
};
pciephy_1: lane@36000 {
- reg = <0x036000 0x130>,
- <0x036200 0x200>,
- <0x036400 0x1dc>;
+ reg = <0x00036000 0x130>,
+ <0x00036200 0x200>,
+ <0x00036400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
@@ -1420,9 +1420,9 @@
};
pciephy_2: lane@37000 {
- reg = <0x037000 0x130>,
- <0x037200 0x200>,
- <0x037400 0x1dc>;
+ reg = <0x00037000 0x130>,
+ <0x00037200 0x200>,
+ <0x00037400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
@@ -1435,7 +1435,7 @@
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
- reg = <0x7410000 0x1c4>;
+ reg = <0x07410000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1452,9 +1452,9 @@
status = "disabled";
ssusb_phy_0: lane@7410200 {
- reg = <0x7410200 0x200>,
- <0x7410400 0x130>,
- <0x7410600 0x1a8>;
+ reg = <0x07410200 0x200>,
+ <0x07410400 0x130>,
+ <0x07410600 0x1a8>;
#phy-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
@@ -1465,7 +1465,7 @@
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
- reg = <0x7411000 0x180>;
+ reg = <0x07411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
@@ -1479,7 +1479,7 @@
hsusb_phy2: phy@7412000 {
compatible = "qcom,msm8996-qusb2-phy";
- reg = <0x7412000 0x180>;
+ reg = <0x07412000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
@@ -1493,7 +1493,7 @@
usb2: usb@76f8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
- reg = <0x76f8800 0x400>;
+ reg = <0x076f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1513,7 +1513,7 @@
dwc3@7600000 {
compatible = "snps,dwc3";
- reg = <0x7600000 0xcc00>;
+ reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
@@ -1522,7 +1522,7 @@
usb3: usb@6af8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
- reg = <0x6af8800 0x400>;
+ reg = <0x06af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -1543,7 +1543,7 @@
dwc3@6a00000 {
compatible = "snps,dwc3";
- reg = <0x6a00000 0xcc00>;
+ reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
@@ -1552,7 +1552,7 @@
vfe_smmu: iommu@da0000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0xda0000 0x10000>;
+ reg = <0x00da0000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -1568,20 +1568,20 @@
camss: camss@a00000 {
compatible = "qcom,msm8996-camss";
- reg = <0xa34000 0x1000>,
- <0xa00030 0x4>,
- <0xa35000 0x1000>,
- <0xa00038 0x4>,
- <0xa36000 0x1000>,
- <0xa00040 0x4>,
- <0xa30000 0x100>,
- <0xa30400 0x100>,
- <0xa30800 0x100>,
- <0xa30c00 0x100>,
- <0xa31000 0x500>,
- <0xa00020 0x10>,
- <0xa10000 0x1000>,
- <0xa14000 0x1000>;
+ reg = <0x00a34000 0x1000>,
+ <0x00a00030 0x4>,
+ <0x00a35000 0x1000>,
+ <0x00a00038 0x4>,
+ <0x00a36000 0x1000>,
+ <0x00a00040 0x4>,
+ <0x00a30000 0x100>,
+ <0x00a30400 0x100>,
+ <0x00a30800 0x100>,
+ <0x00a30c00 0x100>,
+ <0x00a31000 0x500>,
+ <0x00a00020 0x10>,
+ <0x00a10000 0x1000>,
+ <0x00a14000 0x1000>;
reg-names = "csiphy0",
"csiphy0_clk_mux",
"csiphy1",
@@ -1702,7 +1702,7 @@
adreno_smmu: iommu@b40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0xb40000 0x10000>;
+ reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
@@ -1719,7 +1719,7 @@
mdp_smmu: iommu@d00000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0xd00000 0x10000>;
+ reg = <0x00d00000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
@@ -1735,7 +1735,7 @@
lpass_q6_smmu: iommu@1600000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0x1600000 0x20000>;
+ reg = <0x01600000 0x20000>;
#iommu-cells = <1>;
power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
@@ -1922,7 +1922,7 @@
{
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
- reg = <0x9184000 0x32000>;
+ reg = <0x09184000 0x32000>;
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
@@ -1932,7 +1932,7 @@
slim_msm: slim@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
- reg = <0x91c0000 0x2C000>;
+ reg = <0x091c0000 0x2C000>;
reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>,
@@ -1976,7 +1976,7 @@
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
- reg = <0xb00000 0x3f000>;
+ reg = <0x00b00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
@@ -2050,9 +2050,9 @@
mdss: mdss@900000 {
compatible = "qcom,mdss";
- reg = <0x900000 0x1000>,
- <0x9b0000 0x1040>,
- <0x9b8000 0x1040>;
+ reg = <0x00900000 0x1000>,
+ <0x009b0000 0x1040>,
+ <0x009b8000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys",
"vbif_nrt_phys";
@@ -2072,7 +2072,7 @@
mdp: mdp@901000 {
compatible = "qcom,mdp5";
- reg = <0x901000 0x90000>;
+ reg = <0x00901000 0x90000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
@@ -2148,12 +2148,12 @@
hdmi_phy: hdmi-phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
- reg = <0x9a0600 0x1c4>,
- <0x9a0a00 0x124>,
- <0x9a0c00 0x124>,
- <0x9a0e00 0x124>,
- <0x9a1000 0x124>,
- <0x9a1200 0x0c8>;
+ reg = <0x009a0600 0x1c4>,
+ <0x009a0a00 0x124>,
+ <0x009a0c00 0x124>,
+ <0x009a0e00 0x124>,
+ <0x009a1000 0x124>,
+ <0x009a1200 0x0c8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 09/11] arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (7 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 08/11] arm64: dts: qcom: msm8996: Pad addresses Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 10/11] arm64: dts: qcom: db820c: Use regulator names from schematics Bjorn Andersson
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Sort all the nodes by unit address, then name.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 3716 ++++++++++++-------------
1 file changed, 1856 insertions(+), 1860 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6c1a6774396d..60fd8b238c32 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -16,72 +16,19 @@
chosen { };
- memory {
- device_type = "memory";
- /* We expect the bootloader to fill in the reg */
- reg = <0 0 0 0>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- mba_region: mba@91500000 {
- reg = <0x0 0x91500000 0x0 0x200000>;
- no-map;
- };
-
- slpi_region: slpi@90b00000 {
- reg = <0x0 0x90b00000 0x0 0xa00000>;
- no-map;
- };
-
- venus_region: venus@90400000 {
- reg = <0x0 0x90400000 0x0 0x700000>;
- no-map;
- };
-
- adsp_region: adsp@8ea00000 {
- reg = <0x0 0x8ea00000 0x0 0x1a00000>;
- no-map;
- };
-
- mpss_region: mpss@88800000 {
- reg = <0x0 0x88800000 0x0 0x6200000>;
- no-map;
- };
-
- smem_mem: smem-mem@86000000 {
- reg = <0x0 0x86000000 0x0 0x200000>;
- no-map;
- };
-
- memory@85800000 {
- reg = <0x0 0x85800000 0x0 0x800000>;
- no-map;
- };
-
- memory@86200000 {
- reg = <0x0 0x86200000 0x0 0x2600000>;
- no-map;
- };
-
- rmtfs@86700000 {
- compatible = "qcom,rmtfs-mem";
-
- size = <0x0 0x200000>;
- alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
- no-map;
-
- qcom,client-id = <1>;
- qcom,vmid = <15>;
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
};
- zap_shader_region: gpu@8f200000 {
- compatible = "shared-dma-pool";
- reg = <0x0 0x90b00000 0x0 0xa00000>;
- no-map;
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
};
};
@@ -173,307 +120,109 @@
};
};
- thermal-zones {
- cpu0-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ firmware {
+ scm {
+ compatible = "qcom,scm-msm8996";
+ qcom,dload-mode = <&tcsr 0x13000>;
+ };
+ };
- thermal-sensors = <&tsens0 3>;
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
- trips {
- cpu0_alert0: trip-point@0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
- cpu0_crit: cpu_crit {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
- cpu1-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- thermal-sensors = <&tsens0 5>;
+ mba_region: mba@91500000 {
+ reg = <0x0 0x91500000 0x0 0x200000>;
+ no-map;
+ };
- trips {
- cpu1_alert0: trip-point@0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
+ slpi_region: slpi@90b00000 {
+ reg = <0x0 0x90b00000 0x0 0xa00000>;
+ no-map;
+ };
- cpu1_crit: cpu_crit {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
+ venus_region: venus@90400000 {
+ reg = <0x0 0x90400000 0x0 0x700000>;
+ no-map;
};
- cpu2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ adsp_region: adsp@8ea00000 {
+ reg = <0x0 0x8ea00000 0x0 0x1a00000>;
+ no-map;
+ };
- thermal-sensors = <&tsens0 8>;
+ mpss_region: mpss@88800000 {
+ reg = <0x0 0x88800000 0x0 0x6200000>;
+ no-map;
+ };
- trips {
- cpu2_alert0: trip-point@0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
+ smem_mem: smem-mem@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
- cpu2_crit: cpu_crit {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
+ memory@85800000 {
+ reg = <0x0 0x85800000 0x0 0x800000>;
+ no-map;
};
- cpu3-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ memory@86200000 {
+ reg = <0x0 0x86200000 0x0 0x2600000>;
+ no-map;
+ };
- thermal-sensors = <&tsens0 10>;
+ rmtfs@86700000 {
+ compatible = "qcom,rmtfs-mem";
- trips {
- cpu3_alert0: trip-point@0 {
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
+ size = <0x0 0x200000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+ no-map;
- cpu3_crit: cpu_crit {
- temperature = <110000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
};
- gpu-thermal-top {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens1 6>;
-
- trips {
- gpu1_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
+ zap_shader_region: gpu@8f200000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90b00000 0x0 0xa00000>;
+ no-map;
};
+ };
- gpu-thermal-bottom {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
- thermal-sensors = <&tsens1 7>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- trips {
- gpu2_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
- m4m-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
+ mboxes = <&apcs_glb 0>;
- thermal-sensors = <&tsens0 1>;
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8996";
+ qcom,glink-channels = "rpm_requests";
- trips {
- m4m_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- l3-or-venus-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens0 2>;
-
- trips {
- l3_or_venus_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- cluster0-l2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens0 7>;
-
- trips {
- cluster0_l2_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- cluster1-l2-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens0 12>;
-
- trips {
- cluster1_l2_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- camera-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens1 1>;
-
- trips {
- camera_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- q6-dsp-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens1 2>;
-
- trips {
- q6_dsp_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- mem-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens1 3>;
-
- trips {
- mem_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
-
- modemtx-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens1 4>;
-
- trips {
- modemtx_alert0: trip-point@0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
- clocks {
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- clock-output-names = "xo_board";
- };
-
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32764>;
- clock-output-names = "sleep_clk";
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- firmware {
- scm {
- compatible = "qcom,scm-msm8996";
-
- qcom,dload-mode = <&tcsr 0x13000>;
- };
- };
-
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_regs 0 0x1000>;
- #hwlock-cells = <1>;
- };
-
- smem {
- compatible = "qcom,smem";
- memory-region = <&smem_mem>;
- hwlocks = <&tcsr_mutex 3>;
- };
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8996";
- qcom,glink-channels = "rpm_requests";
-
- rpmcc: qcom,rpmcc {
- compatible = "qcom,rpmcc-msm8996";
- #clock-cells = <1>;
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-msm8996";
+ #clock-cells = <1>;
};
rpmpd: power-controller {
@@ -512,1414 +261,1675 @@
};
};
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xffffffff>;
- compatible = "simple-bus";
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
- rpm_msg_ram: memory@68000 {
- compatible = "qcom,rpm-msg-ram";
- reg = <0x00068000 0x6000>;
- };
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
- rng: rng@83000 {
- compatible = "qcom,prng-ee";
- reg = <0x00083000 0x1000>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- clock-names = "core";
- };
+ interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
- tcsr_mutex_regs: syscon@740000 {
- compatible = "syscon";
- reg = <0x00740000 0x20000>;
- };
+ mboxes = <&apcs_glb 10>;
- tsens0: thermal-sensor@4a9000 {
- compatible = "qcom,msm8996-tsens";
- reg = <0x004a9000 0x1000>, /* TM */
- <0x004a8000 0x1000>; /* SROT */
- #qcom,sensors = <13>;
- #thermal-sensor-cells = <1>;
- };
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
- tsens1: thermal-sensor@4ad000 {
- compatible = "qcom,msm8996-tsens";
- reg = <0x004ad000 0x1000>, /* TM */
- <0x004ac000 0x1000>; /* SROT */
- #qcom,sensors = <8>;
- #thermal-sensor-cells = <1>;
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
};
- tcsr: syscon@7a0000 {
- compatible = "qcom,tcsr-msm8996", "syscon";
- reg = <0x007a0000 0x18000>;
- };
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
- intc: interrupt-controller@9bc0000 {
- compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
- #interrupt-cells = <3>;
interrupt-controller;
- #redistributor-regions = <1>;
- redistributor-stride = <0x0 0x40000>;
- reg = <0x09bc0000 0x10000>,
- <0x09c00000 0x100000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
};
+ };
- apcs_glb: mailbox@9820000 {
- compatible = "qcom,msm8996-apcs-hmss-global";
- reg = <0x09820000 0x1000>;
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
- #mbox-cells = <1>;
- };
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
- gcc: clock-controller@300000 {
- compatible = "qcom,gcc-msm8996";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0x00300000 0x90000>;
- };
+ mboxes = <&apcs_glb 14>;
- stm@3002000 {
- compatible = "arm,coresight-stm", "arm,primecell";
- reg = <0x3002000 0x1000>,
- <0x8280000 0x180000>;
- reg-names = "stm-base", "stm-stimulus-base";
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- out-ports {
- port {
- stm_out: endpoint {
- remote-endpoint =
- <&funnel0_in>;
- };
- };
- };
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
};
- tpiu@3020000 {
- compatible = "arm,coresight-tpiu", "arm,primecell";
- reg = <0x3020000 0x1000>;
-
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
- in-ports {
- port {
- tpiu_in: endpoint {
- remote-endpoint =
- <&replicator_out1>;
- };
- };
- };
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
+ };
- funnel@3021000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3021000 0x1000>;
+ smp2p-slpi {
+ compatible = "qcom,smp2p";
+ qcom,smem = <481>, <430>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ mboxes = <&apcs_glb 26>;
- port@7 {
- reg = <7>;
- funnel0_in: endpoint {
- remote-endpoint =
- <&stm_out>;
- };
- };
- };
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <3>;
- out-ports {
- port {
- funnel0_out: endpoint {
- remote-endpoint =
- <&merge_funnel_in0>;
- };
- };
- };
+ smp2p_slpi_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- funnel@3022000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3022000 0x1000>;
+ smp2p_slpi_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+ };
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ pcie_phy: phy@34000 {
+ compatible = "qcom,msm8996-qmp-pcie-phy";
+ reg = <0x00034000 0x488>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- port@6 {
- reg = <6>;
- funnel1_in: endpoint {
- remote-endpoint =
- <&apss_merge_funnel_out>;
- };
- };
- };
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
- out-ports {
- port {
- funnel1_out: endpoint {
- remote-endpoint =
- <&merge_funnel_in1>;
- };
- };
- };
- };
+ resets = <&gcc GCC_PCIE_PHY_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+ reset-names = "phy", "common", "cfg";
+ status = "disabled";
- funnel@3023000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3023000 0x1000>;
+ pciephy_0: lane@35000 {
+ reg = <0x00035000 0x130>,
+ <0x00035200 0x200>,
+ <0x00035400 0x1dc>;
+ #phy-cells = <0>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ clock-output-names = "pcie_0_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "lane0";
+ };
+ pciephy_1: lane@36000 {
+ reg = <0x00036000 0x130>,
+ <0x00036200 0x200>,
+ <0x00036400 0x1dc>;
+ #phy-cells = <0>;
- out-ports {
- port {
- funnel2_out: endpoint {
- remote-endpoint =
- <&merge_funnel_in2>;
- };
- };
+ clock-output-names = "pcie_1_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe1";
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "lane1";
};
- };
- funnel@3025000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3025000 0x1000>;
+ pciephy_2: lane@37000 {
+ reg = <0x00037000 0x130>,
+ <0x00037200 0x200>,
+ <0x00037400 0x1dc>;
+ #phy-cells = <0>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ clock-output-names = "pcie_2_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "pipe2";
+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+ reset-names = "lane2";
+ };
+ };
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ rpm_msg_ram: memory@68000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x00068000 0x6000>;
+ };
- port@0 {
- reg = <0>;
- merge_funnel_in0: endpoint {
- remote-endpoint =
- <&funnel0_out>;
- };
- };
+ qfprom@74000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00074000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
- port@1 {
- reg = <1>;
- merge_funnel_in1: endpoint {
- remote-endpoint =
- <&funnel1_out>;
- };
- };
+ qusb2p_hstx_trim: hstx_trim@24e {
+ reg = <0x24e 0x2>;
+ bits = <5 4>;
+ };
- port@2 {
- reg = <2>;
- merge_funnel_in2: endpoint {
- remote-endpoint =
- <&funnel2_out>;
- };
- };
+ qusb2s_hstx_trim: hstx_trim@24f {
+ reg = <0x24f 0x1>;
+ bits = <1 4>;
};
- out-ports {
- port {
- merge_funnel_out: endpoint {
- remote-endpoint =
- <&etf_in>;
- };
- };
+ gpu_speed_bin: gpu_speed_bin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
};
};
- replicator@3026000 {
- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
- reg = <0x3026000 0x1000>;
-
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ rng: rng@83000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x00083000 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
- in-ports {
- port {
- replicator_in: endpoint {
- remote-endpoint =
- <&etf_out>;
- };
- };
- };
+ gcc: clock-controller@300000 {
+ compatible = "qcom,gcc-msm8996";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x00300000 0x90000>;
+ };
- out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ tsens0: thermal-sensor@4a9000 {
+ compatible = "qcom,msm8996-tsens";
+ reg = <0x004a9000 0x1000>, /* TM */
+ <0x004a8000 0x1000>; /* SROT */
+ #qcom,sensors = <13>;
+ #thermal-sensor-cells = <1>;
+ };
- port@0 {
- reg = <0>;
- replicator_out0: endpoint {
- remote-endpoint =
- <&etr_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- replicator_out1: endpoint {
- remote-endpoint =
- <&tpiu_in>;
- };
- };
- };
+ tsens1: thermal-sensor@4ad000 {
+ compatible = "qcom,msm8996-tsens";
+ reg = <0x004ad000 0x1000>, /* TM */
+ <0x004ac000 0x1000>; /* SROT */
+ #qcom,sensors = <8>;
+ #thermal-sensor-cells = <1>;
};
- etf@3027000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0x3027000 0x1000>;
-
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
-
- in-ports {
- port {
- etf_in: endpoint {
- remote-endpoint =
- <&merge_funnel_out>;
- };
- };
- };
-
- out-ports {
- port {
- etf_out: endpoint {
- remote-endpoint =
- <&replicator_in>;
- };
- };
- };
+ tcsr_mutex_regs: syscon@740000 {
+ compatible = "syscon";
+ reg = <0x00740000 0x20000>;
};
- etr@3028000 {
- compatible = "arm,coresight-tmc", "arm,primecell";
- reg = <0x3028000 0x1000>;
-
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
- arm,scatter-gather;
-
- in-ports {
- port {
- etr_in: endpoint {
- remote-endpoint =
- <&replicator_out0>;
- };
- };
- };
+ tcsr: syscon@7a0000 {
+ compatible = "qcom,tcsr-msm8996", "syscon";
+ reg = <0x007a0000 0x18000>;
};
- debug@3810000 {
- compatible = "arm,coresight-cpu-debug", "arm,primecell";
- reg = <0x3810000 0x1000>;
-
- clocks = <&rpmcc RPM_QDSS_CLK>;
- clock-names = "apb_pclk";
-
- cpu = <&CPU0>;
+ mmcc: clock-controller@8c0000 {
+ compatible = "qcom,mmcc-msm8996";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x008c0000 0x40000>;
+ assigned-clocks = <&mmcc MMPLL9_PLL>,
+ <&mmcc MMPLL1_PLL>,
+ <&mmcc MMPLL3_PLL>,
+ <&mmcc MMPLL4_PLL>,
+ <&mmcc MMPLL5_PLL>;
+ assigned-clock-rates = <624000000>,
+ <810000000>,
+ <980000000>,
+ <960000000>,
+ <825000000>;
};
- etm@3840000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x3840000 0x1000>;
+ mdss: mdss@900000 {
+ compatible = "qcom,mdss";
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ reg = <0x00900000 0x1000>,
+ <0x009b0000 0x1040>,
+ <0x009b8000 0x1040>;
+ reg-names = "mdss_phys",
+ "vbif_phys",
+ "vbif_nrt_phys";
- cpu = <&CPU0>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- out-ports {
- port {
- etm0_out: endpoint {
- remote-endpoint =
- <&apss_funnel0_in0>;
- };
- };
- };
- };
+ interrupt-controller;
+ #interrupt-cells = <1>;
- debug@3910000 {
- compatible = "arm,coresight-cpu-debug", "arm,primecell";
- reg = <0x3910000 0x1000>;
+ clocks = <&mmcc MDSS_AHB_CLK>;
+ clock-names = "iface";
- clocks = <&rpmcc RPM_QDSS_CLK>;
- clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- cpu = <&CPU1>;
- };
+ mdp: mdp@901000 {
+ compatible = "qcom,mdp5";
+ reg = <0x00901000 0x90000>;
+ reg-names = "mdp_phys";
- etm@3940000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x3940000 0x1000>;
+ interrupt-parent = <&mdss>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "iommu",
+ "vsync";
- cpu = <&CPU1>;
+ iommus = <&mdp_smmu 0>;
- out-ports {
- port {
- etm1_out: endpoint {
- remote-endpoint =
- <&apss_funnel0_in1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf3_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
};
};
};
- };
- funnel@39b0000 { /* APSS Funnel 0 */
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x39b0000 0x1000>;
+ hdmi: hdmi-tx@9a0000 {
+ compatible = "qcom,hdmi-tx-8996";
+ reg = <0x009a0000 0x50c>,
+ <0x00070000 0x6158>,
+ <0x009e0000 0xfff>;
+ reg-names = "core_physical",
+ "qfprom_physical",
+ "hdcp_physical";
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ interrupt-parent = <&mdss>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_HDMI_CLK>,
+ <&mmcc MDSS_HDMI_AHB_CLK>,
+ <&mmcc MDSS_EXTPCLK_CLK>;
+ clock-names =
+ "mdp_core",
+ "iface",
+ "core",
+ "alt_iface",
+ "extp";
- port@0 {
- reg = <0>;
- apss_funnel0_in0: endpoint {
- remote-endpoint = <&etm0_out>;
- };
- };
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi_phy";
+ #sound-dai-cells = <1>;
- port@1 {
- reg = <1>;
- apss_funnel0_in1: endpoint {
- remote-endpoint = <&etm1_out>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&mdp5_intf3_out>;
+ };
};
};
};
- out-ports {
- port {
- apss_funnel0_out: endpoint {
- remote-endpoint =
- <&apss_merge_funnel_in0>;
- };
- };
+ hdmi_phy: hdmi-phy@9a0600 {
+ #phy-cells = <0>;
+ compatible = "qcom,hdmi-phy-8996";
+ reg = <0x009a0600 0x1c4>,
+ <0x009a0a00 0x124>,
+ <0x009a0c00 0x124>,
+ <0x009a0e00 0x124>,
+ <0x009a1000 0x124>,
+ <0x009a1200 0x0c8>;
+ reg-names = "hdmi_pll",
+ "hdmi_tx_l0",
+ "hdmi_tx_l1",
+ "hdmi_tx_l2",
+ "hdmi_tx_l3",
+ "hdmi_phy";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&gcc GCC_HDMI_CLKREF_CLK>;
+ clock-names = "iface",
+ "ref";
};
};
+ gpu@b00000 {
+ compatible = "qcom,adreno-530.2", "qcom,adreno";
+ #stream-id-cells = <16>;
- debug@3a10000 {
- compatible = "arm,coresight-cpu-debug", "arm,primecell";
- reg = <0x3a10000 0x1000>;
+ reg = <0x00b00000 0x3f000>;
+ reg-names = "kgsl_3d0_reg_memory";
- clocks = <&rpmcc RPM_QDSS_CLK>;
- clock-names = "apb_pclk";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
- cpu = <&CPU2>;
- };
+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- etm@3a40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x3a40000 0x1000>;
+ clock-names = "core",
+ "iface",
+ "rbbmtimer",
+ "mem",
+ "mem_iface";
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ power-domains = <&mmcc GPU_GDSC>;
+ iommus = <&adreno_smmu 0>;
- cpu = <&CPU2>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
- out-ports {
- port {
- etm2_out: endpoint {
- remote-endpoint =
- <&apss_funnel1_in0>;
- };
+ qcom,gpu-quirk-two-pass-use-wfi;
+ qcom,gpu-quirk-fault-detect-mask;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp-table {
+ compatible ="operating-points-v2";
+
+ /*
+ * 624Mhz and 560Mhz are only available on speed
+ * bin (1 << 0). All the rest are available on
+ * all bins of the hardware
+ */
+ opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-supported-hw = <0x01>;
+ };
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ opp-supported-hw = <0x01>;
+ };
+ opp-510000000 {
+ opp-hz = /bits/ 64 <510000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-401800000 {
+ opp-hz = /bits/ 64 <401800000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-214000000 {
+ opp-hz = /bits/ 64 <214000000>;
+ opp-supported-hw = <0xFF>;
+ };
+ opp-133000000 {
+ opp-hz = /bits/ 64 <133000000>;
+ opp-supported-hw = <0xFF>;
};
};
- };
- debug@3b10000 {
- compatible = "arm,coresight-cpu-debug", "arm,primecell";
- reg = <0x3b10000 0x1000>;
+ zap-shader {
+ memory-region = <&zap_shader_region>;
+ };
+ };
- clocks = <&rpmcc RPM_QDSS_CLK>;
- clock-names = "apb_pclk";
+ msmgpio: pinctrl@1010000 {
+ compatible = "qcom,msm8996-pinctrl";
+ reg = <0x01010000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- cpu = <&CPU3>;
+ spmi_bus: qcom,spmi@400f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0400f000 0x1000>,
+ <0x04400000 0x800000>,
+ <0x04c00000 0x800000>,
+ <0x05800000 0x200000>,
+ <0x0400a000 0x002100>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
};
- etm@3b40000 {
- compatible = "arm,coresight-etm4x", "arm,primecell";
- reg = <0x3b40000 0x1000>;
+ agnoc@0 {
+ power-domains = <&gcc AGGRE0_NOC_GDSC>;
+ compatible = "simple-pm-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ pcie0: pcie@600000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ status = "disabled";
+ power-domains = <&gcc PCIE0_GDSC>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
- cpu = <&CPU3>;
+ reg = <0x00600000 0x2000>,
+ <0x0c000000 0xf1d>,
+ <0x0c000f20 0xa8>,
+ <0x0c100000 0x100000>;
+ reg-names = "parf", "dbi", "elbi","config";
- out-ports {
- port {
- etm3_out: endpoint {
- remote-endpoint =
- <&apss_funnel1_in1>;
- };
- };
- };
- };
+ phys = <&pciephy_0>;
+ phy-names = "pciephy";
- funnel@3bb0000 { /* APSS Funnel 1 */
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3bb0000 0x1000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
+ pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
- port@0 {
- reg = <0>;
- apss_funnel1_in0: endpoint {
- remote-endpoint = <&etm2_out>;
- };
- };
+ linux,pci-domain = <0>;
- port@1 {
- reg = <1>;
- apss_funnel1_in1: endpoint {
- remote-endpoint = <&etm3_out>;
- };
- };
- };
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
- out-ports {
- port {
- apss_funnel1_out: endpoint {
- remote-endpoint =
- <&apss_merge_funnel_in1>;
- };
- };
};
- };
- funnel@3bc0000 {
- compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
- reg = <0x3bc0000 0x1000>;
+ pcie1: pcie@608000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ power-domains = <&gcc PCIE1_GDSC>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
- clock-names = "apb_pclk", "atclk";
+ status = "disabled";
- in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ reg = <0x00608000 0x2000>,
+ <0x0d000000 0xf1d>,
+ <0x0d000f20 0xa8>,
+ <0x0d100000 0x100000>;
- port@0 {
- reg = <0>;
- apss_merge_funnel_in0: endpoint {
- remote-endpoint =
- <&apss_funnel0_out>;
- };
- };
+ reg-names = "parf", "dbi", "elbi","config";
- port@1 {
- reg = <1>;
- apss_merge_funnel_in1: endpoint {
- remote-endpoint =
- <&apss_funnel1_out>;
- };
- };
- };
+ phys = <&pciephy_1>;
+ phy-names = "pciephy";
- out-ports {
- port {
- apss_merge_funnel_out: endpoint {
- remote-endpoint =
- <&funnel1_in>;
- };
- };
- };
- };
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
- kryocc: clock-controller@6400000 {
- compatible = "qcom,apcc-msm8996";
- reg = <0x06400000 0x90000>;
- #clock-cells = <1>;
- };
+ interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- blsp1_uart1: serial@7570000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x07570000 0x1000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
+ pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+
+ linux,pci-domain = <1>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+ };
+
+ pcie2: pcie@610000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ power-domains = <&gcc PCIE2_GDSC>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ status = "disabled";
+ reg = <0x00610000 0x2000>,
+ <0x0e000000 0xf1d>,
+ <0x0e000f20 0xa8>,
+ <0x0e100000 0x100000>;
+
+ reg-names = "parf", "dbi", "elbi","config";
+
+ phys = <&pciephy_2>;
+ phy-names = "pciephy";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+
+ device_type = "pci";
+
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
+ pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+
+ linux,pci-domain = <2>;
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+ <&gcc GCC_PCIE_2_AUX_CLK>,
+ <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+ };
+ };
+
+ ufshc: ufshc@624000 {
+ compatible = "qcom,ufshc";
+ reg = <0x00624000 0x2500>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ phys = <&ufsphy>;
+ phy-names = "ufsphy";
+
+ power-domains = <&gcc UFS_GDSC>;
+
+ clock-names =
+ "core_clk_src",
+ "core_clk",
+ "bus_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro_src",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&gcc UFS_AXI_CLK_SRC>,
+ <&gcc GCC_UFS_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
+ <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&gcc GCC_UFS_AHB_CLK>,
+ <&gcc UFS_ICE_CORE_CLK_SRC>,
+ <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_ICE_CORE_CLK>,
+ <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+ freq-table-hz =
+ <100000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <150000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ lanes-per-direction = <1>;
+ #reset-cells = <1>;
+ status = "disabled";
+
+ ufs_variant {
+ compatible = "qcom,ufs_variant";
+ };
+ };
+
+ ufsphy: phy@627000 {
+ compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
+ reg = <0x00627000 0xda8>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+
+ clock-names = "ref_clk_src", "ref_clk";
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_UFS_CLKREF_CLK>;
+ resets = <&ufshc 0>;
+ status = "disabled";
+ };
+
+ camss: camss@a00000 {
+ compatible = "qcom,msm8996-camss";
+ reg = <0x00a34000 0x1000>,
+ <0x00a00030 0x4>,
+ <0x00a35000 0x1000>,
+ <0x00a00038 0x4>,
+ <0x00a36000 0x1000>,
+ <0x00a00040 0x4>,
+ <0x00a30000 0x100>,
+ <0x00a30400 0x100>,
+ <0x00a30800 0x100>,
+ <0x00a30c00 0x100>,
+ <0x00a31000 0x500>,
+ <0x00a00020 0x10>,
+ <0x00a10000 0x1000>,
+ <0x00a14000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csiphy2",
+ "csiphy2_clk_mux",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0",
+ "vfe1";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 80 0>,
+ <GIC_SPI 296 0>,
+ <GIC_SPI 297 0>,
+ <GIC_SPI 298 0>,
+ <GIC_SPI 299 0>,
+ <GIC_SPI 309 0>,
+ <GIC_SPI 314 0>,
+ <GIC_SPI 315 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "vfe0",
+ "vfe1";
+ power-domains = <&mmcc VFE0_GDSC>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_ISPIF_AHB_CLK>,
+ <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI0_AHB_CLK>,
+ <&mmcc CAMSS_CSI0_CLK>,
+ <&mmcc CAMSS_CSI0PHY_CLK>,
+ <&mmcc CAMSS_CSI0PIX_CLK>,
+ <&mmcc CAMSS_CSI0RDI_CLK>,
+ <&mmcc CAMSS_CSI1_AHB_CLK>,
+ <&mmcc CAMSS_CSI1_CLK>,
+ <&mmcc CAMSS_CSI1PHY_CLK>,
+ <&mmcc CAMSS_CSI1PIX_CLK>,
+ <&mmcc CAMSS_CSI1RDI_CLK>,
+ <&mmcc CAMSS_CSI2_AHB_CLK>,
+ <&mmcc CAMSS_CSI2_CLK>,
+ <&mmcc CAMSS_CSI2PHY_CLK>,
+ <&mmcc CAMSS_CSI2PIX_CLK>,
+ <&mmcc CAMSS_CSI2RDI_CLK>,
+ <&mmcc CAMSS_CSI3_AHB_CLK>,
+ <&mmcc CAMSS_CSI3_CLK>,
+ <&mmcc CAMSS_CSI3PHY_CLK>,
+ <&mmcc CAMSS_CSI3PIX_CLK>,
+ <&mmcc CAMSS_CSI3RDI_CLK>,
+ <&mmcc CAMSS_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_CLK>,
+ <&mmcc CAMSS_CSI_VFE0_CLK>,
+ <&mmcc CAMSS_VFE0_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_STREAM_CLK>,
+ <&mmcc CAMSS_VFE1_CLK>,
+ <&mmcc CAMSS_CSI_VFE1_CLK>,
+ <&mmcc CAMSS_VFE1_AHB_CLK>,
+ <&mmcc CAMSS_VFE1_STREAM_CLK>,
+ <&mmcc CAMSS_VFE_AHB_CLK>,
+ <&mmcc CAMSS_VFE_AXI_CLK>;
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csiphy2_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "csi2_ahb",
+ "csi2",
+ "csi2_phy",
+ "csi2_pix",
+ "csi2_rdi",
+ "csi3_ahb",
+ "csi3",
+ "csi3_phy",
+ "csi3_pix",
+ "csi3_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe0_ahb",
+ "vfe0_stream",
+ "vfe1",
+ "csi_vfe1",
+ "vfe1_ahb",
+ "vfe1_stream",
+ "vfe_ahb",
+ "vfe_axi";
+ iommus = <&vfe_smmu 0>,
+ <&vfe_smmu 1>,
+ <&vfe_smmu 2>,
+ <&vfe_smmu 3>;
status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
- blsp1_spi0: spi@7575000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x07575000 0x600>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_spi0_default>;
- pinctrl-1 = <&blsp1_spi0_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ adreno_smmu: iommu@b40000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0x00b40000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+
+ clocks = <&mmcc GPU_AHB_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+ clock-names = "iface", "bus";
+
+ power-domains = <&mmcc GPU_GDSC>;
};
- blsp2_i2c0: i2c@75b5000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x075b5000 0x1000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c0_default>;
- pinctrl-1 = <&blsp2_i2c0_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ video-codec@c00000 {
+ compatible = "qcom,msm8996-venus";
+ reg = <0x00c00000 0xff000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc VENUS_GDSC>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc VIDEO_MAXI_CLK>;
+ clock-names = "core", "iface", "bus", "mbus";
+ iommus = <&venus_smmu 0x00>,
+ <&venus_smmu 0x01>,
+ <&venus_smmu 0x0a>,
+ <&venus_smmu 0x07>,
+ <&venus_smmu 0x0e>,
+ <&venus_smmu 0x0f>,
+ <&venus_smmu 0x08>,
+ <&venus_smmu 0x09>,
+ <&venus_smmu 0x0b>,
+ <&venus_smmu 0x0c>,
+ <&venus_smmu 0x0d>,
+ <&venus_smmu 0x10>,
+ <&venus_smmu 0x11>,
+ <&venus_smmu 0x21>,
+ <&venus_smmu 0x28>,
+ <&venus_smmu 0x29>,
+ <&venus_smmu 0x2b>,
+ <&venus_smmu 0x2c>,
+ <&venus_smmu 0x2d>,
+ <&venus_smmu 0x31>;
+ memory-region = <&venus_region>;
+ status = "okay";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ };
};
- blsp2_uart1: serial@75b0000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x075b0000 0x1000>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
- <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
+ mdp_smmu: iommu@d00000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0x00d00000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ clocks = <&mmcc SMMU_MDP_AHB_CLK>,
+ <&mmcc SMMU_MDP_AXI_CLK>;
+ clock-names = "iface", "bus";
+
+ power-domains = <&mmcc MDSS_GDSC>;
};
- blsp2_i2c1: i2c@75b6000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x075b6000 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c1_default>;
- pinctrl-1 = <&blsp2_i2c1_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ venus_smmu: arm,smmu-venus@d40000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xd40000 0x20000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
+ clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
+ <&mmcc SMMU_VIDEO_AXI_CLK>;
+ clock-names = "iface", "bus";
+ #iommu-cells = <1>;
+ status = "okay";
};
- blsp2_uart2: serial@75b1000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x075b1000 0x1000>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
- <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
+ vfe_smmu: iommu@da0000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0x00da0000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
+ clocks = <&mmcc SMMU_VFE_AHB_CLK>,
+ <&mmcc SMMU_VFE_AXI_CLK>;
+ clock-names = "iface",
+ "bus";
+ #iommu-cells = <1>;
};
- blsp1_i2c2: i2c@7577000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x07577000 0x1000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_i2c2_default>;
- pinctrl-1 = <&blsp1_i2c2_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ lpass_q6_smmu: iommu@1600000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0x01600000 0x20000>;
+ #iommu-cells = <1>;
+ power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+ clock-names = "iface", "bus";
};
- blsp2_spi5: spi@75ba000{
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x075ba000 0x600>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
- <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_spi5_default>;
- pinctrl-1 = <&blsp2_spi5_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ stm@3002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x3002000 0x1000>,
+ <0x8280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in>;
+ };
+ };
+ };
+ };
+
+ tpiu@3020000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x3020000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ tpiu_in: endpoint {
+ remote-endpoint =
+ <&replicator_out1>;
+ };
+ };
+ };
};
- sdhc2: sdhci@74a4900 {
- status = "disabled";
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ funnel@3021000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3021000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- clock-names = "iface", "core", "xo";
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
- bus-width = <4>;
- };
+ port@7 {
+ reg = <7>;
+ funnel0_in: endpoint {
+ remote-endpoint =
+ <&stm_out>;
+ };
+ };
+ };
- msmgpio: pinctrl@1010000 {
- compatible = "qcom,msm8996-pinctrl";
- reg = <0x01010000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
};
- timer@9840000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "arm,armv7-timer-mem";
- reg = <0x09840000 0x1000>;
- clock-frequency = <19200000>;
+ funnel@3022000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3022000 0x1000>;
- frame@9850000 {
- frame-number = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x09850000 0x1000>,
- <0x09860000 0x1000>;
- };
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- frame@9870000 {
- frame-number = <1>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x09870000 0x1000>;
- status = "disabled";
- };
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- frame@9880000 {
- frame-number = <2>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x09880000 0x1000>;
- status = "disabled";
+ port@6 {
+ reg = <6>;
+ funnel1_in: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
};
- frame@9890000 {
- frame-number = <3>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x09890000 0x1000>;
- status = "disabled";
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in1>;
+ };
+ };
};
+ };
- frame@98a0000 {
- frame-number = <4>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x098a0000 0x1000>;
- status = "disabled";
- };
+ funnel@3023000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3023000 0x1000>;
- frame@98b0000 {
- frame-number = <5>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x098b0000 0x1000>;
- status = "disabled";
- };
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- frame@98c0000 {
- frame-number = <6>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x098c0000 0x1000>;
- status = "disabled";
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
};
};
- spmi_bus: qcom,spmi@400f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x0400f000 0x1000>,
- <0x04400000 0x800000>,
- <0x04c00000 0x800000>,
- <0x05800000 0x200000>,
- <0x0400a000 0x002100>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
+ funnel@3025000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3025000 0x1000>;
- ufsphy: phy@627000 {
- compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
- reg = <0x00627000 0xda8>;
- reg-names = "phy_mem";
- #phy-cells = <0>;
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- clock-names = "ref_clk_src", "ref_clk";
- clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
- <&gcc GCC_UFS_CLKREF_CLK>;
- resets = <&ufshc 0>;
- status = "disabled";
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
};
- ufshc: ufshc@624000 {
- compatible = "qcom,ufshc";
- reg = <0x00624000 0x2500>;
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ replicator@3026000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x3026000 0x1000>;
- phys = <&ufsphy>;
- phy-names = "ufsphy";
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- power-domains = <&gcc UFS_GDSC>;
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint =
+ <&etf_out>;
+ };
+ };
+ };
- clock-names =
- "core_clk_src",
- "core_clk",
- "bus_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro_src",
- "core_clk_unipro",
- "core_clk_ice",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk";
- clocks =
- <&gcc UFS_AXI_CLK_SRC>,
- <&gcc GCC_UFS_AXI_CLK>,
- <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
- <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
- <&gcc GCC_UFS_AHB_CLK>,
- <&gcc UFS_ICE_CORE_CLK_SRC>,
- <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
- <&gcc GCC_UFS_ICE_CORE_CLK>,
- <&rpmcc RPM_SMD_LN_BB_CLK>,
- <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
- freq-table-hz =
- <100000000 200000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>,
- <150000000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- lanes-per-direction = <1>;
- #reset-cells = <1>;
- status = "disabled";
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint =
+ <&etr_in>;
+ };
+ };
- ufs_variant {
- compatible = "qcom,ufs_variant";
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint =
+ <&tpiu_in>;
+ };
+ };
};
};
- mmcc: clock-controller@8c0000 {
- compatible = "qcom,mmcc-msm8996";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- reg = <0x008c0000 0x40000>;
- assigned-clocks = <&mmcc MMPLL9_PLL>,
- <&mmcc MMPLL1_PLL>,
- <&mmcc MMPLL3_PLL>,
- <&mmcc MMPLL4_PLL>,
- <&mmcc MMPLL5_PLL>;
- assigned-clock-rates = <624000000>,
- <810000000>,
- <980000000>,
- <960000000>,
- <825000000>;
- };
+ etf@3027000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3027000 0x1000>;
- qfprom@74000 {
- compatible = "qcom,qfprom";
- reg = <0x00074000 0x8ff>;
- #address-cells = <1>;
- #size-cells = <1>;
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- qusb2p_hstx_trim: hstx_trim@24e {
- reg = <0x24e 0x2>;
- bits = <5 4>;
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
};
- qusb2s_hstx_trim: hstx_trim@24f {
- reg = <0x24f 0x1>;
- bits = <1 4>;
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
};
+ };
- gpu_speed_bin: gpu_speed_bin@133 {
- reg = <0x133 0x1>;
- bits = <5 3>;
+ etr@3028000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3028000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out0>;
+ };
+ };
};
};
- pcie_phy: phy@34000 {
- compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x00034000 0x488>;
- #clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ debug@3810000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3810000 0x1000>;
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
- resets = <&gcc GCC_PCIE_PHY_BCR>,
- <&gcc GCC_PCIE_PHY_COM_BCR>,
- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
- reset-names = "phy", "common", "cfg";
- status = "disabled";
+ cpu = <&CPU0>;
+ };
- pciephy_0: lane@35000 {
- reg = <0x00035000 0x130>,
- <0x00035200 0x200>,
- <0x00035400 0x1dc>;
- #phy-cells = <0>;
+ etm@3840000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3840000 0x1000>;
- clock-output-names = "pcie_0_pipe_clk_src";
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
- };
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- pciephy_1: lane@36000 {
- reg = <0x00036000 0x130>,
- <0x00036200 0x200>,
- <0x00036400 0x1dc>;
- #phy-cells = <0>;
+ cpu = <&CPU0>;
- clock-output-names = "pcie_1_pipe_clk_src";
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe1";
- resets = <&gcc GCC_PCIE_1_PHY_BCR>;
- reset-names = "lane1";
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in0>;
+ };
+ };
};
+ };
- pciephy_2: lane@37000 {
- reg = <0x00037000 0x130>,
- <0x00037200 0x200>,
- <0x00037400 0x1dc>;
- #phy-cells = <0>;
+ debug@3910000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3910000 0x1000>;
- clock-output-names = "pcie_2_pipe_clk_src";
- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
- clock-names = "pipe2";
- resets = <&gcc GCC_PCIE_2_PHY_BCR>;
- reset-names = "lane2";
- };
- };
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
- usb3phy: phy@7410000 {
- compatible = "qcom,msm8996-qmp-usb3-phy";
- reg = <0x07410000 0x1c4>;
- #clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ cpu = <&CPU1>;
+ };
- clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ etm@3940000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3940000 0x1000>;
- resets = <&gcc GCC_USB3_PHY_BCR>,
- <&gcc GCC_USB3PHY_PHY_BCR>;
- reset-names = "phy", "common";
- status = "disabled";
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- ssusb_phy_0: lane@7410200 {
- reg = <0x07410200 0x200>,
- <0x07410400 0x130>,
- <0x07410600 0x1a8>;
- #phy-cells = <0>;
+ cpu = <&CPU1>;
- clock-output-names = "usb3_phy_pipe_clk_src";
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in1>;
+ };
+ };
};
};
- hsusb_phy1: phy@7411000 {
- compatible = "qcom,msm8996-qusb2-phy";
- reg = <0x07411000 0x180>;
- #phy-cells = <0>;
+ funnel@39b0000 { /* APSS Funnel 0 */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x39b0000 0x1000>;
- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_RX1_USB2_CLKREF_CLK>;
- clock-names = "cfg_ahb", "ref";
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
- nvmem-cells = <&qusb2p_hstx_trim>;
- status = "disabled";
- };
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- hsusb_phy2: phy@7412000 {
- compatible = "qcom,msm8996-qusb2-phy";
- reg = <0x07412000 0x180>;
- #phy-cells = <0>;
+ port@0 {
+ reg = <0>;
+ apss_funnel0_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
- clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_RX2_USB2_CLKREF_CLK>;
- clock-names = "cfg_ahb", "ref";
+ port@1 {
+ reg = <1>;
+ apss_funnel0_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
- resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
- nvmem-cells = <&qusb2s_hstx_trim>;
- status = "disabled";
+ out-ports {
+ port {
+ apss_funnel0_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in0>;
+ };
+ };
+ };
};
- usb2: usb@76f8800 {
- compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
- reg = <0x076f8800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ debug@3a10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3a10000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU2>;
+ };
- clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
- <&gcc GCC_USB20_MASTER_CLK>,
- <&gcc GCC_USB20_MOCK_UTMI_CLK>,
- <&gcc GCC_USB20_SLEEP_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+ etm@3a40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3a40000 0x1000>;
- assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
- <&gcc GCC_USB20_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <60000000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- power-domains = <&gcc USB30_GDSC>;
- status = "disabled";
+ cpu = <&CPU2>;
- dwc3@7600000 {
- compatible = "snps,dwc3";
- reg = <0x07600000 0xcc00>;
- interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hsusb_phy2>;
- phy-names = "usb2-phy";
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in0>;
+ };
+ };
};
};
- usb3: usb@6af8800 {
- compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
- reg = <0x06af8800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ debug@3b10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3b10000 0x1000>;
- clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
- <&gcc GCC_USB30_MASTER_CLK>,
- <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
- <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_SLEEP_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
- assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_MASTER_CLK>;
- assigned-clock-rates = <19200000>, <120000000>;
+ cpu = <&CPU3>;
+ };
- power-domains = <&gcc USB30_GDSC>;
- status = "disabled";
+ etm@3b40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3b40000 0x1000>;
- dwc3@6a00000 {
- compatible = "snps,dwc3";
- reg = <0x06a00000 0xcc00>;
- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hsusb_phy1>, <&ssusb_phy_0>;
- phy-names = "usb2-phy", "usb3-phy";
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in1>;
+ };
+ };
};
};
- vfe_smmu: iommu@da0000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0x00da0000 0x10000>;
+ funnel@3bb0000 { /* APSS Funnel 1 */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3bb0000 0x1000>;
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
- #iommu-cells = <1>;
- };
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- camss: camss@a00000 {
- compatible = "qcom,msm8996-camss";
- reg = <0x00a34000 0x1000>,
- <0x00a00030 0x4>,
- <0x00a35000 0x1000>,
- <0x00a00038 0x4>,
- <0x00a36000 0x1000>,
- <0x00a00040 0x4>,
- <0x00a30000 0x100>,
- <0x00a30400 0x100>,
- <0x00a30800 0x100>,
- <0x00a30c00 0x100>,
- <0x00a31000 0x500>,
- <0x00a00020 0x10>,
- <0x00a10000 0x1000>,
- <0x00a14000 0x1000>;
- reg-names = "csiphy0",
- "csiphy0_clk_mux",
- "csiphy1",
- "csiphy1_clk_mux",
- "csiphy2",
- "csiphy2_clk_mux",
- "csid0",
- "csid1",
- "csid2",
- "csid3",
- "ispif",
- "csi_clk_mux",
- "vfe0",
- "vfe1";
- interrupts = <GIC_SPI 78 0>,
- <GIC_SPI 79 0>,
- <GIC_SPI 80 0>,
- <GIC_SPI 296 0>,
- <GIC_SPI 297 0>,
- <GIC_SPI 298 0>,
- <GIC_SPI 299 0>,
- <GIC_SPI 309 0>,
- <GIC_SPI 314 0>,
- <GIC_SPI 315 0>;
- interrupt-names = "csiphy0",
- "csiphy1",
- "csiphy2",
- "csid0",
- "csid1",
- "csid2",
- "csid3",
- "ispif",
- "vfe0",
- "vfe1";
- power-domains = <&mmcc VFE0_GDSC>;
- clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
- <&mmcc CAMSS_ISPIF_AHB_CLK>,
- <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
- <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
- <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
- <&mmcc CAMSS_CSI0_AHB_CLK>,
- <&mmcc CAMSS_CSI0_CLK>,
- <&mmcc CAMSS_CSI0PHY_CLK>,
- <&mmcc CAMSS_CSI0PIX_CLK>,
- <&mmcc CAMSS_CSI0RDI_CLK>,
- <&mmcc CAMSS_CSI1_AHB_CLK>,
- <&mmcc CAMSS_CSI1_CLK>,
- <&mmcc CAMSS_CSI1PHY_CLK>,
- <&mmcc CAMSS_CSI1PIX_CLK>,
- <&mmcc CAMSS_CSI1RDI_CLK>,
- <&mmcc CAMSS_CSI2_AHB_CLK>,
- <&mmcc CAMSS_CSI2_CLK>,
- <&mmcc CAMSS_CSI2PHY_CLK>,
- <&mmcc CAMSS_CSI2PIX_CLK>,
- <&mmcc CAMSS_CSI2RDI_CLK>,
- <&mmcc CAMSS_CSI3_AHB_CLK>,
- <&mmcc CAMSS_CSI3_CLK>,
- <&mmcc CAMSS_CSI3PHY_CLK>,
- <&mmcc CAMSS_CSI3PIX_CLK>,
- <&mmcc CAMSS_CSI3RDI_CLK>,
- <&mmcc CAMSS_AHB_CLK>,
- <&mmcc CAMSS_VFE0_CLK>,
- <&mmcc CAMSS_CSI_VFE0_CLK>,
- <&mmcc CAMSS_VFE0_AHB_CLK>,
- <&mmcc CAMSS_VFE0_STREAM_CLK>,
- <&mmcc CAMSS_VFE1_CLK>,
- <&mmcc CAMSS_CSI_VFE1_CLK>,
- <&mmcc CAMSS_VFE1_AHB_CLK>,
- <&mmcc CAMSS_VFE1_STREAM_CLK>,
- <&mmcc CAMSS_VFE_AHB_CLK>,
- <&mmcc CAMSS_VFE_AXI_CLK>;
- clock-names = "top_ahb",
- "ispif_ahb",
- "csiphy0_timer",
- "csiphy1_timer",
- "csiphy2_timer",
- "csi0_ahb",
- "csi0",
- "csi0_phy",
- "csi0_pix",
- "csi0_rdi",
- "csi1_ahb",
- "csi1",
- "csi1_phy",
- "csi1_pix",
- "csi1_rdi",
- "csi2_ahb",
- "csi2",
- "csi2_phy",
- "csi2_pix",
- "csi2_rdi",
- "csi3_ahb",
- "csi3",
- "csi3_phy",
- "csi3_pix",
- "csi3_rdi",
- "ahb",
- "vfe0",
- "csi_vfe0",
- "vfe0_ahb",
- "vfe0_stream",
- "vfe1",
- "csi_vfe1",
- "vfe1_ahb",
- "vfe1_stream",
- "vfe_ahb",
- "vfe_axi";
- iommus = <&vfe_smmu 0>,
- <&vfe_smmu 1>,
- <&vfe_smmu 2>,
- <&vfe_smmu 3>;
- status = "disabled";
- ports {
+ in-ports {
#address-cells = <1>;
#size-cells = <0>;
- };
- };
-
- adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0x00b40000 0x10000>;
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
+ port@0 {
+ reg = <0>;
+ apss_funnel1_in0: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ port@1 {
+ reg = <1>;
+ apss_funnel1_in1: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
- power-domains = <&mmcc GPU_GDSC>;
+ out-ports {
+ port {
+ apss_funnel1_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in1>;
+ };
+ };
+ };
};
- mdp_smmu: iommu@d00000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0x00d00000 0x10000>;
+ funnel@3bc0000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x3bc0000 0x1000>;
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
- power-domains = <&mmcc MDSS_GDSC>;
- };
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- lpass_q6_smmu: iommu@1600000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0x01600000 0x20000>;
- #iommu-cells = <1>;
- power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+ port@0 {
+ reg = <0>;
+ apss_merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_out>;
+ };
+ };
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+ port@1 {
+ reg = <1>;
+ apss_merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_out>;
+ };
+ };
+ };
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in>;
+ };
+ };
+ };
+ };
+ kryocc: clock-controller@6400000 {
+ compatible = "qcom,apcc-msm8996";
+ reg = <0x06400000 0x90000>;
+ #clock-cells = <1>;
};
- agnoc@0 {
- power-domains = <&gcc AGGRE0_NOC_GDSC>;
- compatible = "simple-pm-bus";
+ usb3: usb@6af8800 {
+ compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
+ reg = <0x06af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- pcie0: pcie@600000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
- status = "disabled";
- power-domains = <&gcc PCIE0_GDSC>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
-
- reg = <0x00600000 0x2000>,
- <0x0c000000 0xf1d>,
- <0x0c000f20 0xa8>,
- <0x0c100000 0x100000>;
- reg-names = "parf", "dbi", "elbi","config";
+ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
- phys = <&pciephy_0>;
- phy-names = "pciephy";
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
- <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ dwc3@6a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x06a00000 0xcc00>;
+ interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
- pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
+ usb3phy: phy@7410000 {
+ compatible = "qcom,msm8996-qmp-usb3-phy";
+ reg = <0x07410000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- linux,pci-domain = <0>;
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+ status = "disabled";
- clock-names = "pipe",
- "aux",
- "cfg",
- "bus_master",
- "bus_slave";
+ ssusb_phy_0: lane@7410200 {
+ reg = <0x07410200 0x200>,
+ <0x07410400 0x130>,
+ <0x07410600 0x1a8>;
+ #phy-cells = <0>;
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
};
+ };
- pcie1: pcie@608000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
- power-domains = <&gcc PCIE1_GDSC>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
+ hsusb_phy1: phy@7411000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x07411000 0x180>;
+ #phy-cells = <0>;
- status = "disabled";
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
- reg = <0x00608000 0x2000>,
- <0x0d000000 0xf1d>,
- <0x0d000f20 0xa8>,
- <0x0d100000 0x100000>;
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2p_hstx_trim>;
+ status = "disabled";
+ };
- reg-names = "parf", "dbi", "elbi","config";
+ hsusb_phy2: phy@7412000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x07412000 0x180>;
+ #phy-cells = <0>;
- phys = <&pciephy_1>;
- phy-names = "pciephy";
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
- <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ nvmem-cells = <&qusb2s_hstx_trim>;
+ status = "disabled";
+ };
- interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ sdhc2: sdhci@74a4900 {
+ status = "disabled";
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
- pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
- linux,pci-domain = <1>;
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+ bus-width = <4>;
+ };
+
+ blsp1_uart1: serial@7570000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x07570000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_spi0: spi@7575000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x07575000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_spi0_default>;
+ pinctrl-1 = <&blsp1_spi0_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
+ blsp1_i2c2: i2c@7577000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x07577000 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c2_default>;
+ pinctrl-1 = <&blsp1_i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- clock-names = "pipe",
- "aux",
- "cfg",
- "bus_master",
- "bus_slave";
- };
+ blsp2_uart1: serial@75b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x075b0000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
- pcie2: pcie@610000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
- power-domains = <&gcc PCIE2_GDSC>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- status = "disabled";
- reg = <0x00610000 0x2000>,
- <0x0e000000 0xf1d>,
- <0x0e000f20 0xa8>,
- <0x0e100000 0x100000>;
+ blsp2_uart2: serial@75b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x075b1000 0x1000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
- reg-names = "parf", "dbi", "elbi","config";
+ blsp2_i2c0: i2c@75b5000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x075b5000 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c0_default>;
+ pinctrl-1 = <&blsp2_i2c0_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- phys = <&pciephy_2>;
- phy-names = "pciephy";
+ blsp2_i2c1: i2c@75b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x075b6000 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c1_default>;
+ pinctrl-1 = <&blsp2_i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
- <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+ blsp2_spi5: spi@75ba000{
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x075ba000 0x600>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_spi5_default>;
+ pinctrl-1 = <&blsp2_spi5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- device_type = "pci";
+ usb2: usb@76f8800 {
+ compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
+ reg = <0x076f8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <60000000>;
- linux,pci-domain = <2>;
- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
- <&gcc GCC_PCIE_2_AUX_CLK>,
- <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
- clock-names = "pipe",
- "aux",
- "cfg",
- "bus_master",
- "bus_slave";
+ dwc3@7600000 {
+ compatible = "snps,dwc3";
+ reg = <0x07600000 0xcc00>;
+ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hsusb_phy2>;
+ phy-names = "usb2-phy";
};
};
- slimbam:dma@9184000
- {
+ slimbam: dma@9184000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0x09184000 0x32000>;
@@ -1935,459 +1945,445 @@
reg = <0x091c0000 0x2C000>;
reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
- #address-cells = <1>;
- #size-cells = <0>;
- ngd@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- tasha_ifd: tas-ifd {
- compatible = "slim217,1a0";
- reg = <0 0>;
- };
-
- wcd9335: codec@1{
- pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
- pinctrl-names = "default";
-
- compatible = "slim217,1a0";
- reg = <1 0>;
-
- interrupt-parent = <&msmgpio>;
- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
- <53 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr1", "intr2";
- interrupt-controller;
- #interrupt-cells = <1>;
- reset-gpios = <&msmgpio 64 0>;
-
- slim-ifc-dev = <&tasha_ifd>;
-
- #sound-dai-cells = <1>;
- };
- };
- };
-
- gpu@b00000 {
- compatible = "qcom,adreno-530.2", "qcom,adreno";
- #stream-id-cells = <16>;
-
- reg = <0x00b00000 0x3f000>;
- reg-names = "kgsl_3d0_reg_memory";
-
- interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&mmcc GPU_GX_GFX3D_CLK>,
- <&mmcc GPU_AHB_CLK>,
- <&mmcc GPU_GX_RBBMTIMER_CLK>,
- <&gcc GCC_BIMC_GFX_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
-
- clock-names = "core",
- "iface",
- "rbbmtimer",
- "mem",
- "mem_iface";
-
- power-domains = <&mmcc GPU_GDSC>;
- iommus = <&adreno_smmu 0>;
-
- nvmem-cells = <&gpu_speed_bin>;
- nvmem-cell-names = "speed_bin";
-
- qcom,gpu-quirk-two-pass-use-wfi;
- qcom,gpu-quirk-fault-detect-mask;
-
- operating-points-v2 = <&gpu_opp_table>;
-
- gpu_opp_table: opp-table {
- compatible ="operating-points-v2";
-
- /*
- * 624Mhz and 560Mhz are only available on speed
- * bin (1 << 0). All the rest are available on
- * all bins of the hardware
- */
- opp-624000000 {
- opp-hz = /bits/ 64 <624000000>;
- opp-supported-hw = <0x01>;
- };
- opp-560000000 {
- opp-hz = /bits/ 64 <560000000>;
- opp-supported-hw = <0x01>;
- };
- opp-510000000 {
- opp-hz = /bits/ 64 <510000000>;
- opp-supported-hw = <0xFF>;
- };
- opp-401800000 {
- opp-hz = /bits/ 64 <401800000>;
- opp-supported-hw = <0xFF>;
- };
- opp-315000000 {
- opp-hz = /bits/ 64 <315000000>;
- opp-supported-hw = <0xFF>;
- };
- opp-214000000 {
- opp-hz = /bits/ 64 <214000000>;
- opp-supported-hw = <0xFF>;
- };
- opp-133000000 {
- opp-hz = /bits/ 64 <133000000>;
- opp-supported-hw = <0xFF>;
+ dmas = <&slimbam 3>, <&slimbam 4>,
+ <&slimbam 5>, <&slimbam 6>;
+ dma-names = "rx", "tx", "tx2", "rx2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ngd@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tasha_ifd: tas-ifd {
+ compatible = "slim217,1a0";
+ reg = <0 0>;
};
- };
- zap-shader {
- memory-region = <&zap_shader_region>;
- };
- };
+ wcd9335: codec@1{
+ pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
+ pinctrl-names = "default";
- mdss: mdss@900000 {
- compatible = "qcom,mdss";
+ compatible = "slim217,1a0";
+ reg = <1 0>;
- reg = <0x00900000 0x1000>,
- <0x009b0000 0x1040>,
- <0x009b8000 0x1040>;
- reg-names = "mdss_phys",
- "vbif_phys",
- "vbif_nrt_phys";
+ interrupt-parent = <&msmgpio>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
+ <53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "intr1", "intr2";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reset-gpios = <&msmgpio 64 0>;
- power-domains = <&mmcc MDSS_GDSC>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ slim-ifc-dev = <&tasha_ifd>;
- interrupt-controller;
- #interrupt-cells = <1>;
+ #sound-dai-cells = <1>;
+ };
+ };
+ };
- clocks = <&mmcc MDSS_AHB_CLK>;
- clock-names = "iface";
+ adsp_pil: remoteproc@9300000 {
+ compatible = "qcom,msm8996-adsp-pil";
+ reg = <0x09300000 0x80000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
- mdp: mdp@901000 {
- compatible = "qcom,mdp5";
- reg = <0x00901000 0x90000>;
- reg-names = "mdp_phys";
+ clocks = <&xo_board>;
+ clock-names = "xo";
- interrupt-parent = <&mdss>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&adsp_region>;
- clocks = <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MDSS_MDP_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>,
- <&mmcc MDSS_VSYNC_CLK>;
- clock-names = "iface",
- "bus",
- "core",
- "iommu",
- "vsync";
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
- iommus = <&mdp_smmu 0>;
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
- ports {
+ label = "lpass";
+ mboxes = <&apcs_glb 8>;
+ qcom,smd-edge = <1>;
+ qcom,remote-pid = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ apr {
+ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
- reg = <0>;
- mdp5_intf3_out: endpoint {
- remote-endpoint = <&hdmi_in>;
+ q6core {
+ reg = <APR_SVC_ADSP_CORE>;
+ compatible = "qcom,q6core";
+ };
+
+ q6afe: q6afe {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ hdmi@1 {
+ reg = <1>;
+ };
};
};
- };
- };
- hdmi: hdmi-tx@9a0000 {
- compatible = "qcom,hdmi-tx-8996";
- reg = <0x009a0000 0x50c>,
- <0x00070000 0x6158>,
- <0x009e0000 0xfff>;
- reg-names = "core_physical",
- "qfprom_physical",
- "hdcp_physical";
+ q6asm: q6asm {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #sound-dai-cells = <1>;
+ iommus = <&lpass_q6_smmu 1>;
+ };
+ };
- interrupt-parent = <&mdss>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ q6adm: q6adm {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
- clocks = <&mmcc MDSS_MDP_CLK>,
- <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_HDMI_CLK>,
- <&mmcc MDSS_HDMI_AHB_CLK>,
- <&mmcc MDSS_EXTPCLK_CLK>;
- clock-names =
- "mdp_core",
- "iface",
- "core",
- "alt_iface",
- "extp";
+ };
+ };
- phys = <&hdmi_phy>;
- phy-names = "hdmi_phy";
- #sound-dai-cells = <1>;
+ apcs_glb: mailbox@9820000 {
+ compatible = "qcom,msm8996-apcs-hmss-global";
+ reg = <0x09820000 0x1000>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ #mbox-cells = <1>;
+ };
- port@0 {
- reg = <0>;
- hdmi_in: endpoint {
- remote-endpoint = <&mdp5_intf3_out>;
- };
- };
- };
+ timer@9840000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x09840000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@9850000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x09850000 0x1000>,
+ <0x09860000 0x1000>;
};
- hdmi_phy: hdmi-phy@9a0600 {
- #phy-cells = <0>;
- compatible = "qcom,hdmi-phy-8996";
- reg = <0x009a0600 0x1c4>,
- <0x009a0a00 0x124>,
- <0x009a0c00 0x124>,
- <0x009a0e00 0x124>,
- <0x009a1000 0x124>,
- <0x009a1200 0x0c8>;
- reg-names = "hdmi_pll",
- "hdmi_tx_l0",
- "hdmi_tx_l1",
- "hdmi_tx_l2",
- "hdmi_tx_l3",
- "hdmi_phy";
+ frame@9870000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x09870000 0x1000>;
+ status = "disabled";
+ };
- clocks = <&mmcc MDSS_AHB_CLK>,
- <&gcc GCC_HDMI_CLKREF_CLK>;
- clock-names = "iface",
- "ref";
+ frame@9880000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x09880000 0x1000>;
+ status = "disabled";
};
- };
- venus_smmu: arm,smmu-venus@d40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
- reg = <0xd40000 0x20000>;
- #global-interrupts = <1>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
- #iommu-cells = <1>;
- status = "okay";
- };
+ frame@9890000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x09890000 0x1000>;
+ status = "disabled";
+ };
- video-codec@c00000 {
- compatible = "qcom,msm8996-venus";
- reg = <0x00c00000 0xff000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&mmcc VENUS_GDSC>;
- clocks = <&mmcc VIDEO_CORE_CLK>,
- <&mmcc VIDEO_AHB_CLK>,
- <&mmcc VIDEO_AXI_CLK>,
- <&mmcc VIDEO_MAXI_CLK>;
- clock-names = "core", "iface", "bus", "mbus";
- iommus = <&venus_smmu 0x00>,
- <&venus_smmu 0x01>,
- <&venus_smmu 0x0a>,
- <&venus_smmu 0x07>,
- <&venus_smmu 0x0e>,
- <&venus_smmu 0x0f>,
- <&venus_smmu 0x08>,
- <&venus_smmu 0x09>,
- <&venus_smmu 0x0b>,
- <&venus_smmu 0x0c>,
- <&venus_smmu 0x0d>,
- <&venus_smmu 0x10>,
- <&venus_smmu 0x11>,
- <&venus_smmu 0x21>,
- <&venus_smmu 0x28>,
- <&venus_smmu 0x29>,
- <&venus_smmu 0x2b>,
- <&venus_smmu 0x2c>,
- <&venus_smmu 0x2d>,
- <&venus_smmu 0x31>;
- memory-region = <&venus_region>;
- status = "okay";
+ frame@98a0000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x098a0000 0x1000>;
+ status = "disabled";
+ };
- video-decoder {
- compatible = "venus-decoder";
- clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
- clock-names = "core";
- power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ frame@98b0000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x098b0000 0x1000>;
+ status = "disabled";
};
- video-encoder {
- compatible = "venus-encoder";
- clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
- clock-names = "core";
- power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ frame@98c0000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x098c0000 0x1000>;
+ status = "disabled";
};
};
+
+ intc: interrupt-controller@9bc0000 {
+ compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+ reg = <0x09bc0000 0x10000>,
+ <0x09c00000 0x100000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
sound: sound {
};
- adsp-pil {
- compatible = "qcom,msm8996-adsp-pil";
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog", "fatal", "ready",
- "handover", "stop-ack";
+ thermal-sensors = <&tsens0 3>;
- clocks = <&xo_board>;
- clock-names = "xo";
+ trips {
+ cpu0_alert0: trip-point@0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
- memory-region = <&adsp_region>;
+ cpu0_crit: cpu_crit {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
- qcom,smem-states = <&adsp_smp2p_out 0>;
- qcom,smem-state-names = "stop";
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- smd-edge {
- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+ thermal-sensors = <&tsens0 5>;
- label = "lpass";
- mboxes = <&apcs_glb 8>;
- qcom,smd-edge = <1>;
- qcom,remote-pid = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- apr {
- power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
- compatible = "qcom,apr-v2";
- qcom,smd-channels = "apr_audio_svc";
- qcom,apr-domain = <APR_DOMAIN_ADSP>;
- #address-cells = <1>;
- #size-cells = <0>;
+ trips {
+ cpu1_alert0: trip-point@0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
- q6core {
- reg = <APR_SVC_ADSP_CORE>;
- compatible = "qcom,q6core";
- };
-
- q6afe: q6afe {
- compatible = "qcom,q6afe";
- reg = <APR_SVC_AFE>;
- q6afedai: dais {
- compatible = "qcom,q6afe-dais";
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <1>;
- hdmi@1 {
- reg = <1>;
- };
- };
+ cpu1_crit: cpu_crit {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
};
+ };
+ };
- q6asm: q6asm {
- compatible = "qcom,q6asm";
- reg = <APR_SVC_ASM>;
- q6asmdai: dais {
- compatible = "qcom,q6asm-dais";
- #sound-dai-cells = <1>;
- iommus = <&lpass_q6_smmu 1>;
- };
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu2_alert0: trip-point@0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
};
- q6adm: q6adm {
- compatible = "qcom,q6adm";
- reg = <APR_SVC_ADM>;
- q6routing: routing {
- compatible = "qcom,q6adm-routing";
- #sound-dai-cells = <0>;
- };
+ cpu2_crit: cpu_crit {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
};
};
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu3_alert0: trip-point@0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu3_crit: cpu_crit {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- };
- adsp-smp2p {
- compatible = "qcom,smp2p";
- qcom,smem = <443>, <429>;
+ gpu-thermal-top {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
+ thermal-sensors = <&tsens1 6>;
- mboxes = <&apcs_glb 10>;
+ trips {
+ gpu1_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
- qcom,local-pid = <0>;
- qcom,remote-pid = <2>;
+ gpu-thermal-bottom {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- adsp_smp2p_out: master-kernel {
- qcom,entry-name = "master-kernel";
- #qcom,smem-state-cells = <1>;
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ gpu2_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
- adsp_smp2p_in: slave-kernel {
- qcom,entry-name = "slave-kernel";
+ m4m-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ m4m_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
- };
- modem-smp2p {
- compatible = "qcom,smp2p";
- qcom,smem = <435>, <428>;
+ l3-or-venus-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+ thermal-sensors = <&tsens0 2>;
- mboxes = <&apcs_glb 14>;
+ trips {
+ l3_or_venus_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
- qcom,local-pid = <0>;
- qcom,remote-pid = <1>;
+ cluster0-l2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- modem_smp2p_out: master-kernel {
- qcom,entry-name = "master-kernel";
- #qcom,smem-state-cells = <1>;
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cluster0_l2_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
- modem_smp2p_in: slave-kernel {
- qcom,entry-name = "slave-kernel";
+ cluster1-l2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cluster1_l2_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
- };
- smp2p-slpi {
- compatible = "qcom,smp2p";
- qcom,smem = <481>, <430>;
+ camera-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+ thermal-sensors = <&tsens1 1>;
- mboxes = <&apcs_glb 26>;
+ trips {
+ camera_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
- qcom,local-pid = <0>;
- qcom,remote-pid = <3>;
+ q6-dsp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
- slpi_smp2p_in: slave-kernel {
- qcom,entry-name = "slave-kernel";
- interrupt-controller;
- #interrupt-cells = <2>;
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ q6_dsp_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
- slpi_smp2p_out: master-kernel {
- qcom,entry-name = "master-kernel";
- #qcom,smem-state-cells = <1>;
+ mem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ mem_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ modemtx-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ modemtx_alert0: trip-point@0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
};
#include "msm8996-pins.dtsi"
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 10/11] arm64: dts: qcom: db820c: Use regulator names from schematics
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (8 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 09/11] arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-10-21 5:13 ` [PATCH 11/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
2019-11-03 8:13 ` [PATCH 00/11] " Vinod Koul
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Update the regulator names in db820c.dtsi to use the names from the
schematics, instead of the made up genric names.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 239 +++++++++++++------
1 file changed, 169 insertions(+), 70 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 6c64deecf950..20d5561cf3e5 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -107,6 +107,26 @@
pinctrl-0 = <&usb3_vbus_det_gpio>;
};
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ vreg_s8a_l3a_input: vreg-s8a-l3a-input {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s8a_l3a_input";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <0>;
+ };
+
wlan_en: wlan-en-1-8v {
pinctrl-names = "default";
pinctrl-0 = <&wlan_en_gpios>;
@@ -187,7 +207,7 @@
};
&camss {
- vdda-supply = <&pm8994_l2>;
+ vdda-supply = <&vreg_l2a_1p25>;
};
&hdmi {
@@ -197,30 +217,30 @@
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
- core-vdda-supply = <&pm8994_l12>;
- core-vcc-supply = <&pm8994_s4>;
+ core-vdda-supply = <&vreg_l12a_1p8>;
+ core-vcc-supply = <&vreg_s4a_1p8>;
};
&hdmi_phy {
status = "okay";
- vddio-supply = <&pm8994_l12>;
- vcca-supply = <&pm8994_l28>;
+ vddio-supply = <&vreg_l12a_1p8>;
+ vcca-supply = <&vreg_l28a_0p925>;
#phy-cells = <0>;
};
&hsusb_phy1 {
status = "okay";
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&hsusb_phy2 {
status = "okay";
- vdda-pll-supply = <&pm8994_l12>;
- vdda-phy-dpdm-supply = <&pm8994_l24>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&mdp {
@@ -493,26 +513,26 @@
status = "okay";
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
- vdda-supply = <&pm8994_l28>;
+ vdda-supply = <&vreg_l28a_0p925>;
};
&pcie1 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
- vdda-supply = <&pm8994_l28>;
+ vdda-supply = <&vreg_l28a_0p925>;
};
&pcie2 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
- vdda-supply = <&pm8994_l28>;
+ vdda-supply = <&vreg_l28a_0p925>;
};
&pcie_phy {
status = "okay";
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
};
&pm8994_gpios {
@@ -656,16 +676,35 @@
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
- vdd_l1-supply = <&pm8994_s3>;
- vdd_l2_l26_l28-supply = <&pm8994_s3>;
- vdd_l3_l11-supply = <&pm8994_s3>;
- vdd_l4_l27_l31-supply = <&pm8994_s3>;
- vdd_l5_l7-supply = <&pm8994_s5>;
- vdd_l14_l15-supply = <&pm8994_s5>;
- vdd_l20_l21-supply = <&pm8994_s5>;
- vdd_l25-supply = <&pm8994_s3>;
-
- pm8994_s3: s3 {
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_s8-supply = <&vph_pwr>;
+ vdd_s9-supply = <&vph_pwr>;
+ vdd_s10-supply = <&vph_pwr>;
+ vdd_s11-supply = <&vph_pwr>;
+ vdd_s12-supply = <&vph_pwr>;
+ vdd_l1-supply = <&vreg_s1b_1p025>;
+ vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
+ vdd_l3_l11-supply = <&vreg_s8a_l3a_input>;
+ vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
+ vdd_l5_l7-supply = <&vreg_s5a_2p15>;
+ vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
+ vdd_l8_l16_l30-supply = <&vph_pwr>;
+ vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
+ vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
+ vdd_l14_l15-supply = <&vreg_s5a_2p15>;
+ vdd_l17_l29-supply = <&vph_pwr_bbyp>;
+ vdd_l20_l21-supply = <&vph_pwr_bbyp>;
+ vdd_l25-supply = <&vreg_s3a_1p3>;
+ vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p3: s3 {
+ regulator-name = "vreg_s3a_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
@@ -674,137 +713,197 @@
* 1.8v required on LS expansion
* for mezzanine boards
*/
- pm8994_s4: s4 {
+ vreg_s4a_1p8: s4 {
+ regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
- pm8994_s5: s5 {
+ vreg_s5a_2p15: s5 {
+ regulator-name = "vreg_s5a_2p15";
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
- pm8994_s7: s7 {
+ vreg_s7a_1p0: s7 {
+ regulator-name = "vreg_s7a_1p0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
- pm8994_l1: l1 {
+ vreg_l1a_1p0: l1 {
+ regulator-name = "vreg_l1a_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
- pm8994_l2: l2 {
+ vreg_l2a_1p25: l2 {
+ regulator-name = "vreg_l2a_1p25";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
};
- pm8994_l3: l3 {
+ vreg_l3a_0p875: l3 {
+ regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
};
- pm8994_l4: l4 {
+ vreg_l4a_1p225: l4 {
+ regulator-name = "vreg_l4a_1p225";
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
- pm8994_l6: l6 {
+ vreg_l6a_1p2: l6 {
+ regulator-name = "vreg_l6a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
- pm8994_l8: l8 {
+ vreg_l8a_1p8: l8 {
+ regulator-name = "vreg_l8a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l9: l9 {
+ vreg_l9a_1p8: l9 {
+ regulator-name = "vreg_l9a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l10: l10 {
+ vreg_l10a_1p8: l10 {
+ regulator-name = "vreg_l10a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l11: l11 {
+ vreg_l11a_1p15: l11 {
+ regulator-name = "vreg_l11a_1p15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
- pm8994_l12: l12 {
+ vreg_l12a_1p8: l12 {
+ regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l13: l13 {
+ vreg_l13a_2p95: l13 {
+ regulator-name = "vreg_l13a_2p95";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
- pm8994_l14: l14 {
+ vreg_l14a_1p8: l14 {
+ regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l15: l15 {
+ vreg_l15a_1p8: l15 {
+ regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l16: l16 {
+ vreg_l16a_2p7: l16 {
+ regulator-name = "vreg_l16a_2p7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
- pm8994_l17: l17 {
+ vreg_l17a_2p8: l17 {
+ regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
- pm8994_l18: l18 {
+ vreg_l18a_2p85: l18 {
+ regulator-name = "vreg_l18a_2p85";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
};
- pm8994_l19: l19 {
+ vreg_l19a_2p8: l19 {
+ regulator-name = "vreg_l19a_2p8";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
- pm8994_l20: l20 {
+ vreg_l20a_2p95: l20 {
+ regulator-name = "vreg_l20a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
- pm8994_l21: l21 {
+ vreg_l21a_2p95: l21 {
+ regulator-name = "vreg_l21a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
- pm8994_l22: l22 {
+ vreg_l22a_3p0: l22 {
+ regulator-name = "vreg_l22a_3p0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- pm8994_l23: l23 {
+ vreg_l23a_2p8: l23 {
+ regulator-name = "vreg_l23a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
- pm8994_l24: l24 {
+ vreg_l24a_3p075: l24 {
+ regulator-name = "vreg_l24a_3p075";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
- pm8994_l25: l25 {
+ vreg_l25a_1p2: l25 {
+ regulator-name = "vreg_l25a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
- pm8994_l27: l27 {
+ vreg_l26a_0p8: l27 {
+ regulator-name = "vreg_l26a_0p8";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
- pm8994_l28: l28 {
+ vreg_l28a_0p925: l28 {
+ regulator-name = "vreg_l28a_0p925";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-allow-set-load;
};
- pm8994_l29: l29 {
+ vreg_l29a_2p8: l29 {
+ regulator-name = "vreg_l29a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
- pm8994_l30: l30 {
+ vreg_l30a_1p8: l30 {
+ regulator-name = "vreg_l30a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
- pm8994_l32: l32 {
+ vreg_l32a_1p8: l32 {
+ regulator-name = "vreg_l32a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ vreg_lvs1a_1p8: lvs1 {
+ regulator-name = "vreg_lvs1a_1p8";
+ };
+
+ vreg_lvs2a_1p8: lvs2 {
+ regulator-name = "vreg_lvs2a_1p8";
+ };
+ };
+
+ pmi8994-regulators {
+ compatible = "qcom,rpm-pmi8994-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_bst_byp-supply = <&vph_pwr>;
+
+ vreg_s1b_1p025: s1 {
+ regulator-name = "vreg_s1b_1p025";
+ regulator-min-microvolt = <1025000>;
+ regulator-max-microvolt = <1025000>;
+ };
+
+ vph_pwr_bbyp: bst-byp {
+ regulator-name = "vph_pwr_bbyp";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3600000>;
+ };
};
};
@@ -814,8 +913,8 @@
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
- vmmc-supply = <&pm8994_l21>;
- vqmmc-supply = <&pm8994_l13>;
+ vmmc-supply = <&vreg_l21a_2p95>;
+ vqmmc-supply = <&vreg_l13a_2p95>;
status = "okay";
};
@@ -908,13 +1007,13 @@
&ufsphy {
status = "okay";
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
- vddp-ref-clk-supply = <&pm8994_l25>;
+ vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
@@ -922,9 +1021,9 @@
&ufshc {
status = "okay";
- vcc-supply = <&pm8994_l20>;
- vccq-supply = <&pm8994_l25>;
- vccq2-supply = <&pm8994_s4>;
+ vcc-supply = <&vreg_l20a_2p95>;
+ vccq-supply = <&vreg_l25a_1p2>;
+ vccq2-supply = <&vreg_s4a_1p8>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
@@ -955,8 +1054,8 @@
&usb3phy {
status = "okay";
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
};
@@ -965,9 +1064,9 @@
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
- vdd-buck-supply = <&pm8994_s4>;
- vdd-buck-sido-supply = <&pm8994_s4>;
- vdd-tx-supply = <&pm8994_s4>;
- vdd-rx-supply = <&pm8994_s4>;
- vdd-io-supply = <&pm8994_s4>;
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 11/11] arm64: dts: qcom: msm8996: Introduce IFC6640
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (9 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 10/11] arm64: dts: qcom: db820c: Use regulator names from schematics Bjorn Andersson
@ 2019-10-21 5:13 ` Bjorn Andersson
2019-11-03 8:13 ` [PATCH 00/11] " Vinod Koul
11 siblings, 0 replies; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21 5:13 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland
Cc: linux-arm-msm, devicetree, linux-kernel
Introduce a base dts for the Inforce 6640 Single Board Computer. This
initial commit boots to console on the uart and provides UFS and SD card
storage support.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 412 +++++++++++++++++++
2 files changed, 413 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6498a1ec893f..b7e33b415e2a 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
+dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
new file mode 100644
index 000000000000..ef8f8ccf837c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/dts-v1/;
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Inforce 6640 Single Board Computer";
+ compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096";
+
+ qcom,msm-id = <291 0x00030001>;
+ qcom,board-id = <0x00010018 0>;
+
+ aliases {
+ serial0 = &blsp2_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ v1p05: v1p05-regulator {
+ compatible = "regulator-fixed";
+ reglator-name = "v1p05";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&v5p0>;
+ };
+
+ v12_poe: v12-poe-regulator {
+ compatible = "regulator-fixed";
+ reglator-name = "v12_poe";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ v3p3: v3p3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v3p3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&v12_poe>;
+ };
+
+ v5p0: v5p0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "v5p0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ vin-supply = <&v12_poe>;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ };
+};
+
+&blsp2_uart1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart1_2pins_default>;
+ pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+};
+
+&msmgpio {
+ sdc2_pins_default: sdc2-pins-default {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ cd {
+ pins = "gpio38";
+ function = "gpio";
+
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+ };
+
+ sdc2_pins_sleep: sdc2-pins-sleep {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cd {
+ pins = "gpio38";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+};
+
+&rpm_requests {
+ pm8994-regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_s8-supply = <&vph_pwr>;
+ vdd_s9-supply = <&vph_pwr>;
+ vdd_s10-supply = <&vph_pwr>;
+ vdd_s11-supply = <&vph_pwr>;
+ vdd_s12-supply = <&vph_pwr>;
+ vdd_l1-supply = <&vreg_s1b_1p025>;
+ vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
+ vdd_l3_l11-supply = <&vreg_s3a_1p3>;
+ vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
+ vdd_l5_l7-supply = <&vreg_s5a_2p15>;
+ vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
+ vdd_l8_l16_l30-supply = <&vph_pwr>;
+ vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
+ vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
+ vdd_l14_l15-supply = <&vph_pwr_bbyp>;
+ vdd_l17_l29-supply = <&vph_pwr_bbyp>;
+ vdd_l20_l21-supply = <&vph_pwr_bbyp>;
+ vdd_l25-supply = <&vreg_s3a_1p3>;
+ vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p3: s3 {
+ regulator-name = "vreg_s3a_1p3";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ vreg_s4a_1p8: s4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vreg_s5a_2p15: s5 {
+ regulator-name = "vreg_s5a_2p15";
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+ vreg_s7a_1p0: s7 {
+ regulator-name = "vreg_s7a_1p0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_l1a_1p0: l1 {
+ regulator-name = "vreg_l1a_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ vreg_l2a_1p25: l2 {
+ regulator-name = "vreg_l2a_1p25";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+ vreg_l3a_0p875: l3 {
+ regulator-name = "vreg_l3a_0p875";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ };
+ vreg_l4a_1p225: l4 {
+ regulator-name = "vreg_l4a_1p225";
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ vreg_l6a_1p2: l6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ vreg_l8a_1p8: l8 {
+ regulator-name = "vreg_l8a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l9a_1p8: l9 {
+ regulator-name = "vreg_l9a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l10a_1p8: l10 {
+ regulator-name = "vreg_l10a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l11a_1p15: l11 {
+ regulator-name = "vreg_l11a_1p15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+ vreg_l12a_1p8: l12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l13a_2p95: l13 {
+ regulator-name = "vreg_l13a_2p95";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ vreg_l14a_1p8: l14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l15a_1p8: l15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l16a_2p7: l16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+ vreg_l17a_2p8: l17 {
+ regulator-name = "vreg_l17a_2p8";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+ vreg_l18a_2p85: l18 {
+ regulator-name = "vreg_l18a_2p85";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+ vreg_l19a_2p8: l19 {
+ regulator-name = "vreg_l19a_2p8";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ vreg_l20a_2p95: l20 {
+ regulator-name = "vreg_l20a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+ vreg_l21a_2p95: l21 {
+ regulator-name = "vreg_l21a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ vreg_l22a_3p0: l22 {
+ regulator-name = "vreg_l22a_3p0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ vreg_l23a_2p8: l23 {
+ regulator-name = "vreg_l23a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ vreg_l24a_3p075: l24 {
+ regulator-name = "vreg_l24a_3p075";
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ vreg_l25a_1p2: l25 {
+ regulator-name = "vreg_l25a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+ vreg_l26a_0p8: l27 {
+ regulator-name = "vreg_l26a_0p8";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+ vreg_l28a_0p925: l28 {
+ regulator-name = "vreg_l28a_0p925";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-allow-set-load;
+ };
+ vreg_l29a_2p8: l29 {
+ regulator-name = "vreg_l29a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ vreg_l30a_1p8: l30 {
+ regulator-name = "vreg_l30a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ vreg_l32a_1p8: l32 {
+ regulator-name = "vreg_l32a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_lvs1a_1p8: lvs1 {
+ regulator-name = "vreg_lvs1a_1p8";
+ };
+
+ vreg_lvs2a_1p8: lvs2 {
+ regulator-name = "vreg_lvs2a_1p8";
+ };
+ };
+
+ pmi8994-regulators {
+ compatible = "qcom,rpm-pmi8994-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_bst_byp-supply = <&vph_pwr>;
+
+ vreg_s1b_1p025: s1 {
+ regulator-name = "vreg_s1b_1p025";
+ regulator-min-microvolt = <1025000>;
+ regulator-max-microvolt = <1025000>;
+ };
+
+ vph_pwr_bbyp: bst-byp {
+ regulator-name = "vph_pwr_bbyp";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3600000>;
+ };
+ };
+};
+
+&sdhc2 {
+ status = "okay";
+
+ bus-width = <4>;
+
+ cd-gpios = <&msmgpio 38 0x1>;
+
+ vmmc-supply = <&vreg_l21a_2p95>;
+ vqmmc-supply = <&vreg_l13a_2p95>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_pins_default>;
+ pinctrl-1 = <&sdc2_pins_sleep>;
+};
+
+&ufshc {
+ status = "okay";
+
+ vcc-supply = <&vreg_l20a_2p95>;
+ vccq-supply = <&vreg_l25a_1p2>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
+};
+
+&ufsphy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+
+ vdda-phy-max-microamp = <18380>;
+ vdda-pll-max-microamp = <9440>;
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
` (10 preceding siblings ...)
2019-10-21 5:13 ` [PATCH 11/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
@ 2019-11-03 8:13 ` Vinod Koul
2019-11-04 4:55 ` Bjorn Andersson
11 siblings, 1 reply; 15+ messages in thread
From: Vinod Koul @ 2019-11-03 8:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
On 20-10-19, 22:13, Bjorn Andersson wrote:
> Refactor msm8996 and db820c in order to make it follow the structure of newer
> platforms, move db820c specific things to db820c.dtsi and then introduce the
> Informace 6640 Single Board Computer.
This has patch 9/11 missing. But rest look good to me.
Acked-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640
2019-11-03 8:13 ` [PATCH 00/11] " Vinod Koul
@ 2019-11-04 4:55 ` Bjorn Andersson
2019-11-04 9:27 ` Vinod Koul
0 siblings, 1 reply; 15+ messages in thread
From: Bjorn Andersson @ 2019-11-04 4:55 UTC (permalink / raw)
To: Vinod Koul
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
On Sun 03 Nov 01:13 PDT 2019, Vinod Koul wrote:
> On 20-10-19, 22:13, Bjorn Andersson wrote:
> > Refactor msm8996 and db820c in order to make it follow the structure of newer
> > platforms, move db820c specific things to db820c.dtsi and then introduce the
> > Informace 6640 Single Board Computer.
>
> This has patch 9/11 missing. But rest look good to me.
>
That's really odd, I copy pasted the recipients into all the patches.
But I'm unable to find it under linux-arm-msm on lore as well.
It's under LKML though, can you please have a look and let me know if I
can extend your ack to patch 9/11 as well?
https://lore.kernel.org/lkml/20191021051322.297560-10-bjorn.andersson@linaro.org/
> Acked-by: Vinod Koul <vkoul@kernel.org>
Thank you for the review Vinod!
Regards,
Bjorn
>
> --
> ~Vinod
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640
2019-11-04 4:55 ` Bjorn Andersson
@ 2019-11-04 9:27 ` Vinod Koul
0 siblings, 0 replies; 15+ messages in thread
From: Vinod Koul @ 2019-11-04 9:27 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
On 03-11-19, 20:55, Bjorn Andersson wrote:
> On Sun 03 Nov 01:13 PDT 2019, Vinod Koul wrote:
>
> > On 20-10-19, 22:13, Bjorn Andersson wrote:
> > > Refactor msm8996 and db820c in order to make it follow the structure of newer
> > > platforms, move db820c specific things to db820c.dtsi and then introduce the
> > > Informace 6640 Single Board Computer.
> >
> > This has patch 9/11 missing. But rest look good to me.
> >
>
> That's really odd, I copy pasted the recipients into all the patches.
> But I'm unable to find it under linux-arm-msm on lore as well.
Yup I can see it there but not on arm-msm. Do you use @linaro smtp to
send. Gmail is known to drop emails to lists on vger..
I use @kernel.org one, havent seen issues on that yet
> It's under LKML though, can you please have a look and let me know if I
> can extend your ack to patch 9/11 as well?
>
> https://lore.kernel.org/lkml/20191021051322.297560-10-bjorn.andersson@linaro.org/
Mostly looks good but the reserve memory doesnt seem sorted by node
(please recheck) and rest looks good so you can add it to that patch as
well :)
--
~Vinod
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-11-04 9:28 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-21 5:13 [PATCH 00/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
2019-10-21 5:13 ` [PATCH 01/11] arm64: dts: qcom: db820c: Move non-soc entries out of /soc Bjorn Andersson
2019-10-21 5:13 ` [PATCH 02/11] arm64: dts: qcom: msm8996: Use node references in db820c Bjorn Andersson
2019-10-21 5:13 ` [PATCH 03/11] arm64: dts: qcom: msm8996: Move regulator consumers to db820c Bjorn Andersson
2019-10-21 5:13 ` [PATCH 04/11] arm64: dts: qcom: msm8996: Move regulators " Bjorn Andersson
2019-10-21 5:13 ` [PATCH 05/11] arm64: dts: qcom: db820c: Group root nodes Bjorn Andersson
2019-10-21 5:13 ` [PATCH 06/11] arm64: dts: qcom: db820c: Sort all nodes Bjorn Andersson
2019-10-21 5:13 ` [PATCH 07/11] arm64: dts: qcom: db820c: Remove pin specific files Bjorn Andersson
2019-10-21 5:13 ` [PATCH 08/11] arm64: dts: qcom: msm8996: Pad addresses Bjorn Andersson
2019-10-21 5:13 ` [PATCH 09/11] arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi Bjorn Andersson
2019-10-21 5:13 ` [PATCH 10/11] arm64: dts: qcom: db820c: Use regulator names from schematics Bjorn Andersson
2019-10-21 5:13 ` [PATCH 11/11] arm64: dts: qcom: msm8996: Introduce IFC6640 Bjorn Andersson
2019-11-03 8:13 ` [PATCH 00/11] " Vinod Koul
2019-11-04 4:55 ` Bjorn Andersson
2019-11-04 9:27 ` Vinod Koul
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