[PATCH v3 00/11] Add device tree support for sc7180

[PATCH v3 00/11] Add device tree support for sc7180

[Rajendra Nayak]

Changes in v3:
* PATCH 2/11: Updated the qup and uart lables to be consistent
with the naming convention followed in sdm845 as suggested
by Matthias
* Dropped 2 patches from v2 which added the new compatible and
binding updates for sc7180 pdc and reused sdm845 compatible instead
as suggested by Marc Z

This series adds DT support for basic peripherals on qualcomm's sc7180 SoC,
drivers for which are already upstream.

The series has a dependency on gcc clock driver patches [1]
to merge first

[1] https://www.spinics.net/lists/linux-clk/msg41851.html

Kiran Gunda (3):
  arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
  arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
  arm64: dts: qcom: sc7180-idp: Add RPMh regulators

Maulik Shah (3):
  arm64: dts: qcom: sc7180: Add cmd_db reserved area
  arm64: dts: qcom: sc7180: Add rpmh-rsc node
  arm64: dts: qcom: sc7180: Add pdc interrupt controller

Rajendra Nayak (3):
  dt-bindings: qcom: Add SC7180 bindings
  arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
  dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

Taniya Das (1):
  arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver

Vivek Gautam (1):
  arm64: dts: sc7180: Add device node for apps_smmu

 .../devicetree/bindings/arm/qcom.yaml         |   2 +
 .../devicetree/bindings/iommu/arm,smmu.txt    |   1 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 arch/arm64/boot/dts/qcom/pm6150.dtsi          |  85 ++++
 arch/arm64/boot/dts/qcom/pm6150l.dtsi         |  47 ++
 arch/arm64/boot/dts/qcom/sc7180-idp.dts       | 256 ++++++++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi          | 459 ++++++++++++++++++
 7 files changed, 851 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 01/11] dt-bindings: qcom: Add SC7180 bindings

[Rajendra Nayak]

Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
Also add a new board type 'idp'

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index e39d8f02e33c..0a60ea051541 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -36,6 +36,7 @@ description: |
   	mdm9615
   	ipq8074
   	sdm845
+  	sc7180
 
   The 'board' element must be one of the following strings:
 
@@ -46,6 +47,7 @@ description: |
   	sbc
   	hk01
   	qrd
+  	idp
 
   The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
   where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 01/11] dt-bindings: qcom: Add SC7180 bindings

[Rob Herring]

On Wed, Oct 23, 2019 at 02:32:09PM +0530, Rajendra Nayak wrote:
> Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
> Also add a new board type 'idp'
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index e39d8f02e33c..0a60ea051541 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -36,6 +36,7 @@ description: |
>    	mdm9615
>    	ipq8074
>    	sdm845
> +  	sc7180

Where's the schema?

>  
>    The 'board' element must be one of the following strings:
>  
> @@ -46,6 +47,7 @@ description: |
>    	sbc
>    	hk01
>    	qrd
> +  	idp
>  
>    The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
>    where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

Re: [PATCH v3 01/11] dt-bindings: qcom: Add SC7180 bindings

[Rajendra Nayak]

On 10/26/2019 1:20 AM, Rob Herring wrote:
> On Wed, Oct 23, 2019 at 02:32:09PM +0530, Rajendra Nayak wrote:
>> Add a SoC string 'sc7180' for the qualcomm SC7180 SoC.
>> Also add a new board type 'idp'
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Reviewed-by: Vinod Koul <vkoul@kernel.org>
>> ---
>>   Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index e39d8f02e33c..0a60ea051541 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -36,6 +36,7 @@ description: |
>>     	mdm9615
>>     	ipq8074
>>     	sdm845
>> +  	sc7180
> 
> Where's the schema?

sorry, missed it, will add when I repost.

> 
>>   
>>     The 'board' element must be one of the following strings:
>>   
>> @@ -46,6 +47,7 @@ description: |
>>     	sbc
>>     	hk01
>>     	qrd
>> +  	idp
>>   
>>     The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
>>     where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
>> -- 
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc

[Rajendra Nayak]

Add skeletal sc7180 SoC dtsi and idp board dts files

Co-developed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v3: 
Updated the qup and uart lables to be consistent
with the naming convention followed in sdm845
as suggested by Matthias

The patch has a dependency on gcc clock driver patches [1]
to merge first

[1] https://www.spinics.net/lists/linux-clk/msg41851.html


 arch/arm64/boot/dts/qcom/Makefile       |   1 +
 arch/arm64/boot/dts/qcom/sc7180-idp.dts |  47 ++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi    | 300 ++++++++++++++++++++++++
 3 files changed, 348 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6498a1ec893f..7a5c2f7fe37f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-asus-novago-tp370ql.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
new file mode 100644
index 000000000000..5ee6eb3e2b99
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 IDP board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7180.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SC7180 IDP";
+	compatible = "qcom,sc7180-idp";
+
+	aliases {
+		serial0 = &uart10;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&uart10 {
+	status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+
+&qup_uart10_default {
+	pinconf-tx {
+		pins = "gpio44";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pinconf-rx {
+		pins = "gpio45";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
new file mode 100644
index 000000000000..084854341ddd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_100>;
+			L2_100: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_200>;
+			L2_200: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_300>;
+			L2_300: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&L2_400>;
+			L2_400: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&L2_500>;
+			L2_500: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			next-level-cache = <&L2_600>;
+			L2_600: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			next-level-cache = <&L2_700>;
+			L2_700: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0  0x10 0>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,gcc-sc7180";
+			reg = <0 0x00100000 0 0x1f0000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x00ac0000 0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			uart10: serial@a88000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart10_default>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		tlmm: pinctrl@3500000 {
+			compatible = "qcom,sc7180-pinctrl";
+			reg = <0 0x03500000 0 0x300000>,
+			      <0 0x03900000 0 0x300000>,
+			      <0 0x03d00000 0 0x300000>;
+			reg-names = "west", "north", "south";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 120>;
+
+			qup_uart10_default: qup-uart10-default {
+				pinmux {
+					pins = "gpio44", "gpio45";
+					function = "qup12";
+				};
+			};
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0 0x17a00000 0 0x10000>,     /* GICD */
+			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			gic-its@17a40000 {
+				compatible = "arm,gic-v3-its";
+				msi-controller;
+				#msi-cells = <1>;
+				reg = <0 0x17a40000 0 0x20000>;
+				status = "disabled";
+			};
+		};
+
+		timer@17c20000{
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0x17c20000 0 0x1000>;
+
+			frame@17c21000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c21000 0 0x1000>,
+				      <0 0x17c22000 0 0x1000>;
+			};
+
+			frame@17c23000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c23000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c25000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c27000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c29000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c2b000 0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0 0x17c2d000 0 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc

[Stephen Boyd]

Quoting Rajendra Nayak (2019-10-23 02:02:10)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> new file mode 100644
> index 000000000000..084854341ddd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -0,0 +1,300 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * SC7180 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <38400000>;
> +                       clock-output-names = "xo_board";

Can you drop the output names property? I think we don't care that the
name is "xo-board" instead of "xo_board" now.

> +                       #clock-cells = <0>;
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <32764>;
> +                       clock-output-names = "sleep_clk";
> +                       #clock-cells = <0>;
> +               };
> +       };
> +
[...]
> +
> +       soc: soc {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges = <0 0 0 0 0x10 0>;
> +               dma-ranges = <0 0 0 0  0x10 0>;

Why the extra space here               ^ ?

> +               compatible = "simple-bus";
> +
> +               gcc: clock-controller@100000 {
> +                       compatible = "qcom,gcc-sc7180";
> +                       reg = <0 0x00100000 0 0x1f0000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +               };
> +
> +               qupv3_id_1: geniqup@ac0000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0 0x00ac0000 0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +
> +                       uart10: serial@a88000 {
> +                               compatible = "qcom,geni-debug-uart";
> +                               reg = <0 0x00a88000 0 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart10_default>;
> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };

Can we not add all the i2c/spi/uart cores here?

> +               };

Re: [PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc

[Rajendra Nayak]

On 10/29/2019 10:19 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-10-23 02:02:10)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> new file mode 100644
>> index 000000000000..084854341ddd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -0,0 +1,300 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * SC7180 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7180.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +       interrupt-parent = <&intc>;
>> +
>> +       #address-cells = <2>;
>> +       #size-cells = <2>;
>> +
>> +       chosen { };
>> +
>> +       clocks {
>> +               xo_board: xo-board {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <38400000>;
>> +                       clock-output-names = "xo_board";
> 
> Can you drop the output names property? I think we don't care that the
> name is "xo-board" instead of "xo_board" now.

sure, will do.

> 
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               sleep_clk: sleep-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <32764>;
>> +                       clock-output-names = "sleep_clk";
>> +                       #clock-cells = <0>;
>> +               };
>> +       };
>> +
> [...]
>> +
>> +       soc: soc {
>> +               #address-cells = <2>;
>> +               #size-cells = <2>;
>> +               ranges = <0 0 0 0 0x10 0>;
>> +               dma-ranges = <0 0 0 0  0x10 0>;
> 
> Why the extra space here               ^ ?

typo, will fix.

> 
>> +               compatible = "simple-bus";
>> +
>> +               gcc: clock-controller@100000 {
>> +                       compatible = "qcom,gcc-sc7180";
>> +                       reg = <0 0x00100000 0 0x1f0000>;
>> +                       #clock-cells = <1>;
>> +                       #reset-cells = <1>;
>> +                       #power-domain-cells = <1>;
>> +               };
>> +
>> +               qupv3_id_1: geniqup@ac0000 {
>> +                       compatible = "qcom,geni-se-qup";
>> +                       reg = <0 0x00ac0000 0 0x6000>;
>> +                       clock-names = "m-ahb", "s-ahb";
>> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> +                       #address-cells = <2>;
>> +                       #size-cells = <2>;
>> +                       ranges;
>> +                       status = "disabled";
>> +
>> +                       uart10: serial@a88000 {
>> +                               compatible = "qcom,geni-debug-uart";
>> +                               reg = <0 0x00a88000 0 0x4000>;
>> +                               clock-names = "se";
>> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> +                               pinctrl-names = "default";
>> +                               pinctrl-0 = <&qup_uart10_default>;
>> +                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>> +                               status = "disabled";
>> +                       };
> 
> Can we not add all the i2c/spi/uart cores here?

I see that these nodes are posted now [1].
Will pull it in as part of this series so it can be reviewed together.

[1] https://lkml.org/lkml/2019/10/31/63

-- 
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[PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

[Rajendra Nayak]

Add the soc specific compatible for sc7180 smmu-500

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..347869807cf2 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -30,6 +30,7 @@ conditions.
                   Qcom SoCs implementing "arm,mmu-500" must also include,
                   as below, SoC-specific compatibles:
                   "qcom,sdm845-smmu-500", "arm,mmu-500"
+                  "qcom,sc7180-smmu-500", "arm,mmu-500"
 
 - reg           : Base address and size of the SMMU.
 
-- 
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of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

[Rob Herring]

On Wed, Oct 23, 2019 at 02:32:11PM +0530, Rajendra Nayak wrote:
> Add the soc specific compatible for sc7180 smmu-500
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> ---
>  Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..347869807cf2 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -30,6 +30,7 @@ conditions.
>                    Qcom SoCs implementing "arm,mmu-500" must also include,
>                    as below, SoC-specific compatibles:
>                    "qcom,sdm845-smmu-500", "arm,mmu-500"
> +                  "qcom,sc7180-smmu-500", "arm,mmu-500"

This is now a schema file in my tree.

>  
>  - reg           : Base address and size of the SMMU.
>  
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

[Rajendra Nayak]

On 10/26/2019 1:21 AM, Rob Herring wrote:
> On Wed, Oct 23, 2019 at 02:32:11PM +0530, Rajendra Nayak wrote:
>> Add the soc specific compatible for sc7180 smmu-500
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Joerg Roedel <joro@8bytes.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> index 3133f3ba7567..347869807cf2 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> @@ -30,6 +30,7 @@ conditions.
>>                     Qcom SoCs implementing "arm,mmu-500" must also include,
>>                     as below, SoC-specific compatibles:
>>                     "qcom,sdm845-smmu-500", "arm,mmu-500"
>> +                  "qcom,sc7180-smmu-500", "arm,mmu-500"
> 
> This is now a schema file in my tree.

sure, will rebase on your for-next when I repost.

> 
>>   
>>   - reg           : Base address and size of the SMMU.
>>   
>> -- 
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

[Stephen Boyd]

Quoting Rajendra Nayak (2019-10-23 02:02:11)
> Add the soc specific compatible for sc7180 smmu-500
> 
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> ---
>  Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..347869807cf2 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -30,6 +30,7 @@ conditions.
>                    Qcom SoCs implementing "arm,mmu-500" must also include,
>                    as below, SoC-specific compatibles:
>                    "qcom,sdm845-smmu-500", "arm,mmu-500"
> +                  "qcom,sc7180-smmu-500", "arm,mmu-500"

Please sort.

Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC

[Rajendra Nayak]

On 10/29/2019 10:12 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-10-23 02:02:11)
>> Add the soc specific compatible for sc7180 smmu-500
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Joerg Roedel <joro@8bytes.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> index 3133f3ba7567..347869807cf2 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
>> @@ -30,6 +30,7 @@ conditions.
>>                     Qcom SoCs implementing "arm,mmu-500" must also include,
>>                     as below, SoC-specific compatibles:
>>                     "qcom,sdm845-smmu-500", "arm,mmu-500"
>> +                  "qcom,sc7180-smmu-500", "arm,mmu-500"
> 
> Please sort.

thanks, will do.

> 

-- 
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of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 04/11] arm64: dts: sc7180: Add device node for apps_smmu

[Rajendra Nayak]

From: Vivek Gautam <vivek.gautam@codeaurora.org>

Adding device node for APPS SMMU that is connected to
devices such as display, video, usb, mmc, etc. on SC7180
chipset.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 084854341ddd..f17684148595 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -211,6 +211,94 @@
 			};
 		};
 
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
+			reg = <0 0x15000000 0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			#address-cells = <2>;
-- 
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of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 05/11] arm64: dts: qcom: sc7180: Add cmd_db reserved area

[Rajendra Nayak]

From: Maulik Shah <mkshah@codeaurora.org>

Command_db provides mapping for resource key and address managed
by remote processor. Add cmd_db reserved memory area.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f17684148595..dfa49ef2bce0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -32,6 +32,18 @@
 		};
 	};
 
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cmd_db: reserved-memory@80820000 {
+			reg = <0x0 0x80820000 0x0 0x20000>;
+			compatible = "qcom,cmd-db";
+			no-map;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
-- 
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of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 05/11] arm64: dts: qcom: sc7180: Add cmd_db reserved area

[Sibi Sankar]

On 2019-10-23 14:32, Rajendra Nayak wrote:
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Command_db provides mapping for resource key and address managed
> by remote processor. Add cmd_db reserved memory area.
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f17684148595..dfa49ef2bce0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -32,6 +32,18 @@
>  		};
>  	};
> 
> +	reserved_memory: reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		cmd_db: reserved-memory@80820000 {

aop_cmd_db_mem: memory@80820000 {
please use ^^ instead

> +			reg = <0x0 0x80820000 0x0 0x20000>;
> +			compatible = "qcom,cmd-db";
> +			no-map;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <2>;
>  		#size-cells = <0>;

-- 
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v3 05/11] arm64: dts: qcom: sc7180: Add cmd_db reserved area

[Rajendra Nayak]

On 10/23/2019 5:46 PM, Sibi Sankar wrote:
> On 2019-10-23 14:32, Rajendra Nayak wrote:
>> From: Maulik Shah <mkshah@codeaurora.org>
>>
>> Command_db provides mapping for resource key and address managed
>> by remote processor. Add cmd_db reserved memory area.
>>
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index f17684148595..dfa49ef2bce0 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -32,6 +32,18 @@
>>          };
>>      };
>>
>> +    reserved_memory: reserved-memory {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        cmd_db: reserved-memory@80820000 {
> 
> aop_cmd_db_mem: memory@80820000 {
> please use ^^ instead

right, I thought I looked up sm8150.dtsi to make sure
the labeling for various things is consistent, but
maybe i didn't. Will fix. Thanks.

> 
>> +            reg = <0x0 0x80820000 0x0 0x20000>;
>> +            compatible = "qcom,cmd-db";
>> +            no-map;
>> +        };
>> +    };
>> +
>>      cpus {
>>          #address-cells = <2>;
>>          #size-cells = <0>;
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 06/11] arm64: dts: qcom: sc7180: Add rpmh-rsc node

[Rajendra Nayak]

From: Maulik Shah <mkshah@codeaurora.org>

Add device bindings for the application processor's rsc. The rsc
contains the TCS that are used for communicating with the hardened
resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index dfa49ef2bce0..04808a07d7da 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -388,6 +389,24 @@
 				status = "disabled";
 			};
 		};
+
+		apps_rsc: rsc@18200000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x18200000 0 0x10000>,
+			      <0 0x18210000 0 0x10000>,
+			      <0 0x18220000 0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS  2>,
+					  <SLEEP_TCS   3>,
+					  <WAKE_TCS    3>,
+					  <CONTROL_TCS 1>;
+		};
 	};
 
 	timer {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device

[Rajendra Nayak]

From: Kiran Gunda <kgunda@codeaurora.org>

Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 04808a07d7da..6584ac6e6c7b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -224,6 +224,25 @@
 			};
 		};
 
+		spmi_bus: spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0 0xc440000 0 0x1100>,
+			      <0 0xc600000 0 0x2000000>,
+			      <0 0xe600000 0 0x100000>,
+			      <0 0xe700000 0 0xa0000>,
+			      <0 0xc40a000 0 0x26000>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			cell-index = <0>;
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device

[Stephen Boyd]

Quoting Rajendra Nayak (2019-10-23 02:02:15)
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 04808a07d7da..6584ac6e6c7b 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -224,6 +224,25 @@
>                         };
>                 };
>  
> +               spmi_bus: spmi@c440000 {
> +                       compatible = "qcom,spmi-pmic-arb";
> +                       reg = <0 0xc440000 0 0x1100>,

Please pad out the registers to 8 numbers. See sdm845.

> +                             <0 0xc600000 0 0x2000000>,
> +                             <0 0xe600000 0 0x100000>,
> +                             <0 0xe700000 0 0xa0000>,
> +                             <0 0xc40a000 0 0x26000>;
> +                       reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +                       interrupt-names = "periph_irq";
> +                       interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;

This is different than sdm845. I guess pdc is working?

> +                       qcom,ee = <0>;
> +                       qcom,channel = <0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <4>;
> +                       cell-index = <0>;
> +               };
> +

Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device

[kgunda]

On 2019-10-29 22:11, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-10-23 02:02:15)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 04808a07d7da..6584ac6e6c7b 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -224,6 +224,25 @@
>>                         };
>>                 };
>> 
>> +               spmi_bus: spmi@c440000 {
>> +                       compatible = "qcom,spmi-pmic-arb";
>> +                       reg = <0 0xc440000 0 0x1100>,
> 
> Please pad out the registers to 8 numbers. See sdm845.
Ok.. Will address it in the next series.
> 
>> +                             <0 0xc600000 0 0x2000000>,
>> +                             <0 0xe600000 0 0x100000>,
>> +                             <0 0xe700000 0 0xa0000>,
>> +                             <0 0xc40a000 0 0x26000>;
>> +                       reg-names = "core", "chnls", "obsrvr", "intr", 
>> "cnfg";
>> +                       interrupt-names = "periph_irq";
>> +                       interrupts-extended = <&pdc 1 
>> IRQ_TYPE_LEVEL_HIGH>;
> 
> This is different than sdm845. I guess pdc is working?
> 
Yes. For SDM845 pdc controller support was not yet added. That's why 
still the GIC interrupt is used.
Where as for SC7180 the same is added with 
https://lore.kernel.org/patchwork/patch/1143335/.

Yes. pdc is working.

>> +                       qcom,ee = <0>;
>> +                       qcom,channel = <0>;
>> +                       #address-cells = <1>;
>> +                       #size-cells = <1>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <4>;
>> +                       cell-index = <0>;
>> +               };
>> +

Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device

[Stephen Boyd]

Quoting kgunda@codeaurora.org (2019-10-29 23:06:43)
> On 2019-10-29 22:11, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2019-10-23 02:02:15)
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
> >> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> >> index 04808a07d7da..6584ac6e6c7b 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> >> @@ -224,6 +224,25 @@
> >>                         };
> >>                 };
> >> 
> >> +               spmi_bus: spmi@c440000 {
> >> +                       compatible = "qcom,spmi-pmic-arb";
> >> +                       reg = <0 0xc440000 0 0x1100>,
> > 
> > Please pad out the registers to 8 numbers. See sdm845.
> Ok.. Will address it in the next series.
> > 
> >> +                             <0 0xc600000 0 0x2000000>,
> >> +                             <0 0xe600000 0 0x100000>,
> >> +                             <0 0xe700000 0 0xa0000>,
> >> +                             <0 0xc40a000 0 0x26000>;
> >> +                       reg-names = "core", "chnls", "obsrvr", "intr", 
> >> "cnfg";
> >> +                       interrupt-names = "periph_irq";
> >> +                       interrupts-extended = <&pdc 1 
> >> IRQ_TYPE_LEVEL_HIGH>;
> > 
> > This is different than sdm845. I guess pdc is working?
> > 
> Yes. For SDM845 pdc controller support was not yet added. That's why 
> still the GIC interrupt is used.
> Where as for SC7180 the same is added with 
> https://lore.kernel.org/patchwork/patch/1143335/.
> 
> Yes. pdc is working.

Cool. The patch that adds pdc to the DT should come before this one
then. In reality, it would be better if it was all squashed down into
one big commit that just introduces the SoC file and one commit for
PMICs and then one commit for the idp board. Then we don't have this
ordering problem.

Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device

[Rajendra Nayak]

On 10/30/2019 8:07 PM, Stephen Boyd wrote:
> Quoting kgunda@codeaurora.org (2019-10-29 23:06:43)
>> On 2019-10-29 22:11, Stephen Boyd wrote:
>>> Quoting Rajendra Nayak (2019-10-23 02:02:15)
>>>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> index 04808a07d7da..6584ac6e6c7b 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>>>> @@ -224,6 +224,25 @@
>>>>                          };
>>>>                  };
>>>>
>>>> +               spmi_bus: spmi@c440000 {
>>>> +                       compatible = "qcom,spmi-pmic-arb";
>>>> +                       reg = <0 0xc440000 0 0x1100>,
>>>
>>> Please pad out the registers to 8 numbers. See sdm845.
>> Ok.. Will address it in the next series.
>>>
>>>> +                             <0 0xc600000 0 0x2000000>,
>>>> +                             <0 0xe600000 0 0x100000>,
>>>> +                             <0 0xe700000 0 0xa0000>,
>>>> +                             <0 0xc40a000 0 0x26000>;
>>>> +                       reg-names = "core", "chnls", "obsrvr", "intr",
>>>> "cnfg";
>>>> +                       interrupt-names = "periph_irq";
>>>> +                       interrupts-extended = <&pdc 1
>>>> IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> This is different than sdm845. I guess pdc is working?
>>>
>> Yes. For SDM845 pdc controller support was not yet added. That's why
>> still the GIC interrupt is used.
>> Where as for SC7180 the same is added with
>> https://lore.kernel.org/patchwork/patch/1143335/.
>>
>> Yes. pdc is working.
> 
> Cool. The patch that adds pdc to the DT should come before this one
> then. In reality, it would be better if it was all squashed down into
> one big commit that just introduces the SoC file and one commit for
> PMICs and then one commit for the idp board. Then we don't have this
> ordering problem.

I'll fix the ordering issues when I respin.
I could squash all of the patches touching the SoC dtsi, but given the
authorship for each varies, I will keep it as is perhaps.

-- 
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of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals

[Rajendra Nayak]

From: Kiran Gunda <kgunda@codeaurora.org>

Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other
PMIC infra modules.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/pm6150.dtsi    | 85 +++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/pm6150l.dtsi   | 47 ++++++++++++++
 arch/arm64/boot/dts/qcom/sc7180-idp.dts |  2 +
 3 files changed, 134 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi

diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
new file mode 100644
index 000000000000..20eb928e5ce3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
+
+&spmi_bus {
+	pm6150_lsid0: pmic@0 {
+		compatible = "qcom,pm6150", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm6150_pon: pon@800 {
+			compatible = "qcom,pm8998-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
+		pm6150_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm6150_adc: adc@3100 {
+			compatible = "qcom,spmi-adc5";
+			reg = <0x3100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			adc-chan@ADC5_DIE_TEMP {
+				reg = <ADC5_DIE_TEMP>;
+				label = "die_temp";
+			};
+		};
+
+		pm6150_gpio: gpios@c000 {
+			compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
+			reg = <0xc000 0xa00>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+				     <0 0xc1 0 IRQ_TYPE_NONE>,
+				     <0 0xc2 0 IRQ_TYPE_NONE>,
+				     <0 0xc3 0 IRQ_TYPE_NONE>,
+				     <0 0xc4 0 IRQ_TYPE_NONE>,
+				     <0 0xc5 0 IRQ_TYPE_NONE>,
+				     <0 0xc6 0 IRQ_TYPE_NONE>,
+				     <0 0xc7 0 IRQ_TYPE_NONE>,
+				     <0 0xc8 0 IRQ_TYPE_NONE>,
+				     <0 0xc9 0 IRQ_TYPE_NONE>;
+
+			interrupt-names = "pm6150_gpio1", "pm6150_gpio2",
+					"pm6150_gpio3", "pm6150_gpio4",
+					"pm6150_gpio5", "pm6150_gpio6",
+					"pm6150_gpio7", "pm6150_gpio8",
+					"pm6150_gpio9", "pm6150_gpio10";
+		};
+	};
+
+	pm6150_lsid1: pmic@1 {
+		compatible = "qcom,pm6150", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
new file mode 100644
index 000000000000..b17bb1af9367
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	pm6150l_lsid4: pmic@4 {
+		compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm6150l_gpios: gpios@c000 {
+			compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
+			reg = <0xc000 0xc00>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <4 0xc0 0 IRQ_TYPE_NONE>,
+				     <4 0xc1 0 IRQ_TYPE_NONE>,
+				     <4 0xc2 0 IRQ_TYPE_NONE>,
+				     <4 0xc3 0 IRQ_TYPE_NONE>,
+				     <4 0xc4 0 IRQ_TYPE_NONE>,
+				     <4 0xc5 0 IRQ_TYPE_NONE>,
+				     <4 0xc6 0 IRQ_TYPE_NONE>,
+				     <4 0xc7 0 IRQ_TYPE_NONE>,
+				     <4 0xc8 0 IRQ_TYPE_NONE>,
+				     <4 0xc9 0 IRQ_TYPE_NONE>,
+				     <4 0xca 0 IRQ_TYPE_NONE>,
+				     <4 0xcb 0 IRQ_TYPE_NONE>;
+
+			interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2",
+					"pm6150l_gpio3", "pm6150l_gpio4",
+					"pm6150l_gpio5", "pm6150l_gpio6",
+					"pm6150l_gpio7", "pm6150l_gpio8",
+					"pm6150l_gpio9", "pm6150l_gpio10",
+					"pm6150l_gpio11", "pm6150l_gpio12";
+		};
+	};
+
+	pm6150l_lsid5: pmic@5 {
+		compatible = "qcom,pm6150l", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 5ee6eb3e2b99..be42ae9d2d9d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -8,6 +8,8 @@
 /dts-v1/;
 
 #include "sc7180.dtsi"
+#include "pm6150.dtsi"
+#include "pm6150l.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. SC7180 IDP";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals

[Stephen Boyd]

Quoting Rajendra Nayak (2019-10-23 02:02:16)
> diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
> new file mode 100644
> index 000000000000..20eb928e5ce3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2019, The Linux Foundation. All rights reserved.
> +
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +&spmi_bus {
> +       pm6150_lsid0: pmic@0 {
> +               compatible = "qcom,pm6150", "qcom,spmi-pmic";
> +               reg = <0x0 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               pm6150_pon: pon@800 {
> +                       compatible = "qcom,pm8998-pon";
> +                       reg = <0x800>;
> +                       mode-bootloader = <0x2>;
> +                       mode-recovery = <0x1>;

Can this have status = "disabled"? Or is the idea that if the pmic power
button isn't used it should be disabled in the board dts file?

> +
> +                       pwrkey {
> +                               compatible = "qcom,pm8941-pwrkey";
> +                               interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
> +                               debounce = <15625>;
> +                               bias-pull-up;
> +                               linux,code = <KEY_POWER>;
> +                       };
> +               };
> +
> +               pm6150_temp: temp-alarm@2400 {
> +                       compatible = "qcom,spmi-temp-alarm";
> +                       reg = <0x2400>;
> +                       interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
> +                       io-channel-names = "thermal";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
> +               pm6150_adc: adc@3100 {
> +                       compatible = "qcom,spmi-adc5";
> +                       reg = <0x3100>;
> +                       interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       #io-channel-cells = <1>;
> +
> +                       adc-chan@ADC5_DIE_TEMP {
> +                               reg = <ADC5_DIE_TEMP>;
> +                               label = "die_temp";
> +                       };
> +               };
> +
> +               pm6150_gpio: gpios@c000 {
> +                       compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
> +                       reg = <0xc000 0xa00>;

Drop the size?

> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc1 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc2 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc3 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc4 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc5 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc6 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc7 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc8 0 IRQ_TYPE_NONE>,
> +                                    <0 0xc9 0 IRQ_TYPE_NONE>;

Isn't this supposed to go away?

> +
> +                       interrupt-names = "pm6150_gpio1", "pm6150_gpio2",
> +                                       "pm6150_gpio3", "pm6150_gpio4",
> +                                       "pm6150_gpio5", "pm6150_gpio6",
> +                                       "pm6150_gpio7", "pm6150_gpio8",
> +                                       "pm6150_gpio9", "pm6150_gpio10";

And this? And have gpio-ranges and use the irqdomain work. Basically,
should look like pm8998.

> +               };
> +       };
> +
> +       pm6150_lsid1: pmic@1 {
> +               compatible = "qcom,pm6150", "qcom,spmi-pmic";
> +               reg = <0x1 SPMI_USID>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +};

Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals

[kgunda]

On 2019-10-29 22:08, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-10-23 02:02:16)
>> diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi 
>> b/arch/arm64/boot/dts/qcom/pm6150.dtsi
>> new file mode 100644
>> index 000000000000..20eb928e5ce3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
>> @@ -0,0 +1,85 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +// Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> +
>> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
>> +#include <dt-bindings/input/linux-event-codes.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/spmi/spmi.h>
>> +#include <dt-bindings/thermal/thermal.h>
>> +
>> +&spmi_bus {
>> +       pm6150_lsid0: pmic@0 {
>> +               compatible = "qcom,pm6150", "qcom,spmi-pmic";
>> +               reg = <0x0 SPMI_USID>;
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +
>> +               pm6150_pon: pon@800 {
>> +                       compatible = "qcom,pm8998-pon";
>> +                       reg = <0x800>;
>> +                       mode-bootloader = <0x2>;
>> +                       mode-recovery = <0x1>;
> 
> Can this have status = "disabled"? Or is the idea that if the pmic 
> power
> button isn't used it should be disabled in the board dts file?
> 
Yes. The idea is to go with latter option. Disable it in the board dts 
file if the
pmic power button is not used.
>> +
>> +                       pwrkey {
>> +                               compatible = "qcom,pm8941-pwrkey";
>> +                               interrupts = <0x0 0x8 0 
>> IRQ_TYPE_EDGE_BOTH>;
>> +                               debounce = <15625>;
>> +                               bias-pull-up;
>> +                               linux,code = <KEY_POWER>;
>> +                       };
>> +               };
>> +
>> +               pm6150_temp: temp-alarm@2400 {
>> +                       compatible = "qcom,spmi-temp-alarm";
>> +                       reg = <0x2400>;
>> +                       interrupts = <0x0 0x24 0x0 
>> IRQ_TYPE_EDGE_RISING>;
>> +                       io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
>> +                       io-channel-names = "thermal";
>> +                       #thermal-sensor-cells = <0>;
>> +               };
>> +
>> +               pm6150_adc: adc@3100 {
>> +                       compatible = "qcom,spmi-adc5";
>> +                       reg = <0x3100>;
>> +                       interrupts = <0x0 0x31 0x0 
>> IRQ_TYPE_EDGE_RISING>;
>> +                       #address-cells = <1>;
>> +                       #size-cells = <0>;
>> +                       #io-channel-cells = <1>;
>> +
>> +                       adc-chan@ADC5_DIE_TEMP {
>> +                               reg = <ADC5_DIE_TEMP>;
>> +                               label = "die_temp";
>> +                       };
>> +               };
>> +
>> +               pm6150_gpio: gpios@c000 {
>> +                       compatible = "qcom,pm6150-gpio", 
>> "qcom,spmi-gpio";
>> +                       reg = <0xc000 0xa00>;
> 
> Drop the size?
> 
Will drop it in next series.
>> +                       gpio-controller;
>> +                       #gpio-cells = <2>;
>> +                       interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc1 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc2 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc3 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc4 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc5 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc6 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc7 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc8 0 IRQ_TYPE_NONE>,
>> +                                    <0 0xc9 0 IRQ_TYPE_NONE>;
> 
> Isn't this supposed to go away?
> 
Yes. We can remove them if we want to go with the way done for pm8998.
>> +
>> +                       interrupt-names = "pm6150_gpio1", 
>> "pm6150_gpio2",
>> +                                       "pm6150_gpio3", 
>> "pm6150_gpio4",
>> +                                       "pm6150_gpio5", 
>> "pm6150_gpio6",
>> +                                       "pm6150_gpio7", 
>> "pm6150_gpio8",
>> +                                       "pm6150_gpio9", 
>> "pm6150_gpio10";
> 
> And this? And have gpio-ranges and use the irqdomain work. Basically,
> should look like pm8998.
Ok.. We can go ahead with the pm8998 way as well. We will address it in 
next series.
> 
>> +               };
>> +       };
>> +
>> +       pm6150_lsid1: pmic@1 {
>> +               compatible = "qcom,pm6150", "qcom,spmi-pmic";
>> +               reg = <0x1 SPMI_USID>;
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +       };
>> +};

Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals

[Stephen Boyd]

Quoting kgunda@codeaurora.org (2019-10-30 00:06:05)
> On 2019-10-29 22:08, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2019-10-23 02:02:16)
> >> diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi 
> >> b/arch/arm64/boot/dts/qcom/pm6150.dtsi
> >> new file mode 100644
> >> index 000000000000..20eb928e5ce3
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
> >> @@ -0,0 +1,85 @@
> >> +// SPDX-License-Identifier: BSD-3-Clause
> >> +// Copyright (c) 2019, The Linux Foundation. All rights reserved.
> >> +
> >> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> >> +#include <dt-bindings/input/linux-event-codes.h>
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >> +#include <dt-bindings/spmi/spmi.h>
> >> +#include <dt-bindings/thermal/thermal.h>
> >> +
> >> +&spmi_bus {
> >> +       pm6150_lsid0: pmic@0 {
> >> +               compatible = "qcom,pm6150", "qcom,spmi-pmic";
> >> +               reg = <0x0 SPMI_USID>;
> >> +               #address-cells = <1>;
> >> +               #size-cells = <0>;
> >> +
> >> +               pm6150_pon: pon@800 {
> >> +                       compatible = "qcom,pm8998-pon";
> >> +                       reg = <0x800>;
> >> +                       mode-bootloader = <0x2>;
> >> +                       mode-recovery = <0x1>;
> > 
> > Can this have status = "disabled"? Or is the idea that if the pmic 
> > power
> > button isn't used it should be disabled in the board dts file?
> > 
> Yes. The idea is to go with latter option. Disable it in the board dts 
> file if the
> pmic power button is not used.

Ok. Thanks.

> >> +
> >> +                       interrupt-names = "pm6150_gpio1", 
> >> "pm6150_gpio2",
> >> +                                       "pm6150_gpio3", 
> >> "pm6150_gpio4",
> >> +                                       "pm6150_gpio5", 
> >> "pm6150_gpio6",
> >> +                                       "pm6150_gpio7", 
> >> "pm6150_gpio8",
> >> +                                       "pm6150_gpio9", 
> >> "pm6150_gpio10";
> > 
> > And this? And have gpio-ranges and use the irqdomain work. Basically,
> > should look like pm8998.
> Ok.. We can go ahead with the pm8998 way as well. We will address it in 
> next series.

Yes please use the pm8998 way..

[PATCH v3 09/11] arm64: dts: qcom: sc7180-idp: Add RPMh regulators

[Rajendra Nayak]

From: Kiran Gunda <kgunda@codeaurora.org>

Add the rpmh regulators for the sc7180 idp platform. This platform
consists of PMIC PM6150 and PM6150l

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++
 1 file changed, 207 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index be42ae9d2d9d..e0724ef3317d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sc7180.dtsi"
 #include "pm6150.dtsi"
 #include "pm6150l.dtsi"
@@ -24,6 +25,212 @@
 	};
 };
 
+&apps_rsc {
+	pm6150-rpmh-regulators {
+		compatible = "qcom,pm6150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s1a_1p1: smps1 {
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1128000>;
+		};
+
+		vreg_s4a_1p0: smps4 {
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <1120000>;
+		};
+
+		vreg_s5a_2p0: smps5 {
+			regulator-min-microvolt = <1744000>;
+			regulator-max-microvolt = <2040000>;
+		};
+
+		vreg_l1a_1p2: ldo1 {
+			regulator-min-microvolt = <1178000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l2a_1p0: ldo2 {
+			regulator-min-microvolt = <944000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l3a_1p0: ldo3 {
+			regulator-min-microvolt = <968000>;
+			regulator-max-microvolt = <1064000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l4a_0p8: ldo4 {
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <928000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l5a_2p7: ldo5 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l6a_0p6: ldo6 {
+			regulator-min-microvolt = <568000>;
+			regulator-max-microvolt = <648000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l9a_0p6: ldo9 {
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l10a_1p8: ldo10 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1832000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l11a_1p8: ldo11 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l12a_1p8: ldo12 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1952000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l13a_1p8: ldo13 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l14a_1p8: ldo14 {
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1832000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l15a_1p8: ldo15 {
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l16a_2p7: ldo16 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l17a_3p0: ldo17 {
+			regulator-min-microvolt = <2920000>;
+			regulator-max-microvolt = <3232000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l18a_2p8: ldo18 {
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l19a_2p9: ldo19 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	pm6150l-rpmh-regulators {
+		compatible = "qcom,pm6150l-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_s8c_1p3: smps8 {
+			regulator-min-microvolt = <1120000>;
+			regulator-max-microvolt = <1408000>;
+		};
+
+		vreg_l1c_1p8: ldo1 {
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <1984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l2c_1p3: ldo2 {
+			regulator-min-microvolt = <1168000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l3c_1p2: ldo3 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l4c_1p8: ldo4 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l5c_1p8: ldo5 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l6c_2p9: ldo6 {
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l7c_3p0: ldo7 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l8c_1p8: ldo8 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l9c_2p9: ldo9 {
+			regulator-min-microvolt = <2952000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l10c_3p3: ldo10 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_l11c_3p3: ldo11 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+		};
+	};
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 10/11] arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver

[Rajendra Nayak]

From: Taniya Das <tdas@codeaurora.org>

Add node for rpmhcc clock driver.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6584ac6e6c7b..f2981ada578f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -175,6 +176,9 @@
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sc7180";
 			reg = <0 0x00100000 0 0x1f0000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-names = "bi_tcxo", "bi_tcxo_ao";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
@@ -425,6 +429,13 @@
 					  <SLEEP_TCS   3>,
 					  <WAKE_TCS    3>,
 					  <CONTROL_TCS 1>;
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sc7180-rpmh-clk";
+				clocks = <&xo_board>;
+				clock-names = "xo";
+				#clock-cells = <1>;
+			};
 		};
 	};
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Rajendra Nayak]

From: Maulik Shah <mkshah@codeaurora.org>

Add pdc interrupt controller for sc7180

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
v3:
Used the qcom,sdm845-pdc compatible for pdc node

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f2981ada578f..07ea393c2b5f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -184,6 +184,16 @@
 			#power-domain-cells = <1>;
 		};
 
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sdm845-pdc";
+			reg = <0 0xb220000 0 0x30000>;
+			qcom,pdc-ranges = <0 480 15>, <17 497 98>,
+					  <119 634 4>, <124 639 1>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
 		qupv3_id_1: geniqup@ac0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x00ac0000 0 0x6000>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Matthias Kaehlcke]

Hi Rajendra/Maulik,

On Wed, Oct 23, 2019 at 02:32:19PM +0530, Rajendra Nayak wrote:
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Add pdc interrupt controller for sc7180
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> v3:
> Used the qcom,sdm845-pdc compatible for pdc node
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f2981ada578f..07ea393c2b5f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -184,6 +184,16 @@
>  			#power-domain-cells = <1>;
>  		};
>  
> +		pdc: interrupt-controller@b220000 {

Aren't the nodes supposed to be ordered by address as for SDM845?
If so this node should be added after 'qupv3_id_1: geniqup@ac0000',
not before.

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Rajendra Nayak]

On 10/26/2019 1:17 AM, Matthias Kaehlcke wrote:
> Hi Rajendra/Maulik,
> 
> On Wed, Oct 23, 2019 at 02:32:19PM +0530, Rajendra Nayak wrote:
>> From: Maulik Shah <mkshah@codeaurora.org>
>>
>> Add pdc interrupt controller for sc7180
>>
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
>> v3:
>> Used the qcom,sdm845-pdc compatible for pdc node
>>
>>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index f2981ada578f..07ea393c2b5f 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -184,6 +184,16 @@
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		pdc: interrupt-controller@b220000 {
> 
> Aren't the nodes supposed to be ordered by address as for SDM845?
> If so this node should be added after 'qupv3_id_1: geniqup@ac0000',
> not before.

yes, indeed. my sorting seems to have gone wrong. Will fix and repost.
thanks

> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Stephen Boyd]

Quoting Rajendra Nayak (2019-10-23 02:02:19)
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Add pdc interrupt controller for sc7180
> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
> v3:
> Used the qcom,sdm845-pdc compatible for pdc node

Everything else isn't doing the weird old compatible thing. Why not just
add the new compatible and update the driver? I guess I'll have to go
read the history.

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Matthias Kaehlcke]

On Tue, Oct 29, 2019 at 09:50:40AM -0700, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-10-23 02:02:19)
> > From: Maulik Shah <mkshah@codeaurora.org>
> > 
> > Add pdc interrupt controller for sc7180
> > 
> > Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> > ---
> > v3:
> > Used the qcom,sdm845-pdc compatible for pdc node
> 
> Everything else isn't doing the weird old compatible thing. Why not just
> add the new compatible and update the driver? I guess I'll have to go
> read the history.

Marc Zyngier complained  on v2 about the churn from adding compatible
strings for identical components, and I kinda see his point.

I agree that using the 'sdm845' compatible string for sc7180 is odd too.
Maybe we should introduce SoC independent compatible strings for IP blocks
that are shared across multiple SoCs? If differentiation is needed SoC
specific strings can be added.

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Rajendra Nayak]

On 10/31/2019 1:20 AM, Matthias Kaehlcke wrote:
> On Tue, Oct 29, 2019 at 09:50:40AM -0700, Stephen Boyd wrote:
>> Quoting Rajendra Nayak (2019-10-23 02:02:19)
>>> From: Maulik Shah <mkshah@codeaurora.org>
>>>
>>> Add pdc interrupt controller for sc7180
>>>
>>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>>> ---
>>> v3:
>>> Used the qcom,sdm845-pdc compatible for pdc node
>>
>> Everything else isn't doing the weird old compatible thing. Why not just
>> add the new compatible and update the driver? I guess I'll have to go
>> read the history.
> 
> Marc Zyngier complained  on v2 about the churn from adding compatible
> strings for identical components, and I kinda see his point.
> 
> I agree that using the 'sdm845' compatible string for sc7180 is odd too.
> Maybe we should introduce SoC independent compatible strings for IP blocks
> that are shared across multiple SoCs? If differentiation is needed SoC
> specific strings can be added.

Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid
confusion.


-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Bjorn Andersson]

On Sun 03 Nov 22:17 PST 2019, Rajendra Nayak wrote:

> 
> 
> On 10/31/2019 1:20 AM, Matthias Kaehlcke wrote:
> > On Tue, Oct 29, 2019 at 09:50:40AM -0700, Stephen Boyd wrote:
> > > Quoting Rajendra Nayak (2019-10-23 02:02:19)
> > > > From: Maulik Shah <mkshah@codeaurora.org>
> > > > 
> > > > Add pdc interrupt controller for sc7180
> > > > 
> > > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> > > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> > > > ---
> > > > v3:
> > > > Used the qcom,sdm845-pdc compatible for pdc node
> > > 
> > > Everything else isn't doing the weird old compatible thing. Why not just
> > > add the new compatible and update the driver? I guess I'll have to go
> > > read the history.
> > 
> > Marc Zyngier complained  on v2 about the churn from adding compatible
> > strings for identical components, and I kinda see his point.
> > 
> > I agree that using the 'sdm845' compatible string for sc7180 is odd too.
> > Maybe we should introduce SoC independent compatible strings for IP blocks
> > that are shared across multiple SoCs? If differentiation is needed SoC
> > specific strings can be added.
> 
> Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid
> confusion.
> 

I agree,

compatible = "qcom,sc7180-pdc", "qcom,pdc";

is the way to go.

Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen
issues/variations/erratas with one or the other platform in the future.

Regards,
Bjorn

> 
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Rajendra Nayak]

On 11/4/2019 12:03 PM, Bjorn Andersson wrote:
> On Sun 03 Nov 22:17 PST 2019, Rajendra Nayak wrote:
> 
>>
>>
>> On 10/31/2019 1:20 AM, Matthias Kaehlcke wrote:
>>> On Tue, Oct 29, 2019 at 09:50:40AM -0700, Stephen Boyd wrote:
>>>> Quoting Rajendra Nayak (2019-10-23 02:02:19)
>>>>> From: Maulik Shah <mkshah@codeaurora.org>
>>>>>
>>>>> Add pdc interrupt controller for sc7180
>>>>>
>>>>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>>>>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>>>>> ---
>>>>> v3:
>>>>> Used the qcom,sdm845-pdc compatible for pdc node
>>>>
>>>> Everything else isn't doing the weird old compatible thing. Why not just
>>>> add the new compatible and update the driver? I guess I'll have to go
>>>> read the history.
>>>
>>> Marc Zyngier complained  on v2 about the churn from adding compatible
>>> strings for identical components, and I kinda see his point.
>>>
>>> I agree that using the 'sdm845' compatible string for sc7180 is odd too.
>>> Maybe we should introduce SoC independent compatible strings for IP blocks
>>> that are shared across multiple SoCs? If differentiation is needed SoC
>>> specific strings can be added.
>>
>> Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid
>> confusion.
>>
> 
> I agree,
> 
> compatible = "qcom,sc7180-pdc", "qcom,pdc";
> 
> is the way to go.

I wasn't planning on adding a qcom,sc7180-pdc, but instead just use the
qcom,pdc one for sc7180.

> 
> Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen
> issues/variations/erratas with one or the other platform in the future.

That was the intention of adding qcom,sc7180-pdc in the first place,
but Marc Zyngier was not happy with the churn, given there aren't really
any variations or erratas that we know of.

> 
> Regards,
> Bjorn
> 
>>
>> -- 
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Bjorn Andersson]

On Sun 03 Nov 22:56 PST 2019, Rajendra Nayak wrote:

> 
> 
> On 11/4/2019 12:03 PM, Bjorn Andersson wrote:
> > On Sun 03 Nov 22:17 PST 2019, Rajendra Nayak wrote:
> > 
> > > 
> > > 
> > > On 10/31/2019 1:20 AM, Matthias Kaehlcke wrote:
> > > > On Tue, Oct 29, 2019 at 09:50:40AM -0700, Stephen Boyd wrote:
> > > > > Quoting Rajendra Nayak (2019-10-23 02:02:19)
> > > > > > From: Maulik Shah <mkshah@codeaurora.org>
> > > > > > 
> > > > > > Add pdc interrupt controller for sc7180
> > > > > > 
> > > > > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> > > > > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> > > > > > ---
> > > > > > v3:
> > > > > > Used the qcom,sdm845-pdc compatible for pdc node
> > > > > 
> > > > > Everything else isn't doing the weird old compatible thing. Why not just
> > > > > add the new compatible and update the driver? I guess I'll have to go
> > > > > read the history.
> > > > 
> > > > Marc Zyngier complained  on v2 about the churn from adding compatible
> > > > strings for identical components, and I kinda see his point.
> > > > 
> > > > I agree that using the 'sdm845' compatible string for sc7180 is odd too.
> > > > Maybe we should introduce SoC independent compatible strings for IP blocks
> > > > that are shared across multiple SoCs? If differentiation is needed SoC
> > > > specific strings can be added.
> > > 
> > > Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid
> > > confusion.
> > > 
> > 
> > I agree,
> > 
> > compatible = "qcom,sc7180-pdc", "qcom,pdc";
> > 
> > is the way to go.
> 
> I wasn't planning on adding a qcom,sc7180-pdc, but instead just use the
> qcom,pdc one for sc7180.
> 
> > 
> > Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen
> > issues/variations/erratas with one or the other platform in the future.
> 
> That was the intention of adding qcom,sc7180-pdc in the first place,
> but Marc Zyngier was not happy with the churn, given there aren't really
> any variations or erratas that we know of.
> 

Right, but by putting both compatibles in the dts and the generic one in
the driver we avoid the driver churn and we're future compatible.

And given that we haven't yet added the qcom,sdm845-pdc node to the
sdm845.dtsi we don't need to maintain the qcom,sdm845-pdc in the driver.
So switch qcom,sdm845-pdc to qcom,pdc in qcom-pdc.c.

Regards,
Bjorn

> > 
> > Regards,
> > Bjorn
> > 
> > > 
> > > -- 
> > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> > > of Code Aurora Forum, hosted by The Linux Foundation
> 
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller

[Stephen Boyd]

Quoting Bjorn Andersson (2019-11-03 23:10:27)
> 
> Right, but by putting both compatibles in the dts and the generic one in
> the driver we avoid the driver churn and we're future compatible.
> 
> And given that we haven't yet added the qcom,sdm845-pdc node to the
> sdm845.dtsi we don't need to maintain the qcom,sdm845-pdc in the driver.
> So switch qcom,sdm845-pdc to qcom,pdc in qcom-pdc.c.
> 

I like this plan!