From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A916CA9EAF for ; Sun, 27 Oct 2019 14:45:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A071214AF for ; Sun, 27 Oct 2019 14:45:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572187559; bh=ziUIhoTUlVs+k2kjQOK0Igcf1cXP8akgwKfUmLFB3oE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=QXRK0qRZfMIjJBf84Ky7bLGvnNGCmO4RZmuZSqwKGHa567v2FpY+QPDAuNjJBS/6I AyHi7ujXwrr6XueXs5pTcQ8hMtWTHqvU3l6fl+dGI0u+yzvsXbRSpJCyLrQ7r8sWTg vsT7LHC71QJtyO35ZNdFAW2t+snVvS2ra5X14aI8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727464AbfJ0Op6 (ORCPT ); Sun, 27 Oct 2019 10:45:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:38680 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726817AbfJ0Op5 (ORCPT ); Sun, 27 Oct 2019 10:45:57 -0400 Received: from localhost.localdomain (82-132-239-15.dab.02.net [82.132.239.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A52C521726; Sun, 27 Oct 2019 14:45:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572187556; bh=ziUIhoTUlVs+k2kjQOK0Igcf1cXP8akgwKfUmLFB3oE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bmDWKx111VIJookxfnPaqIwSYt3TIqs/phurD5G99zuGIko69LXYKpg3GODSkeyDj oEX8UjUnZOgsa2b09U09jZE28AurDSv+WldN1C0Qk65WVoodvUxbclIkjkl01xXjQQ 3HLG+OdWNs8HAxcBxZjeA8r1K7iqR73/nKDoJd/g= From: Marc Zyngier To: kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Cc: Eric Auger , James Morse , Julien Thierry , Suzuki K Poulose , Thomas Gleixner , Jason Cooper , Lorenzo Pieralisi , Andrew Murray , Zenghui Yu , Jayachandran C , Robert Richter Subject: [PATCH v2 27/36] irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks Date: Sun, 27 Oct 2019 14:42:25 +0000 Message-Id: <20191027144234.8395-28-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191027144234.8395-1-maz@kernel.org> References: <20191027144234.8395-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To implement the get/set_irqchip_state callbacks (limited to the PENDING state), we have to use a particular set of hacks: - Reading the pending state is done by using a pair of new redistributor registers (GICR_VSGIR, GICR_VSGIPENDR), which allow the 16 interrupts state to be retrieved. - Setting the pending state is done by generating it as we'd otherwise do for a guest (writing to GITS_SGIR) - Clearing the pending state is done by emiting a VSGI command with the "clear" bit set. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 56 ++++++++++++++++++++++++++++++ include/linux/irqchip/arm-gic-v3.h | 14 ++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b9cef419f006..58dd497dc274 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3690,11 +3690,67 @@ static int its_sgi_set_affinity(struct irq_data *d, return -EINVAL; } +static int its_sgi_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool state) +{ + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (state) { + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); + struct its_node *its = find_4_1_its(); + u64 val; + + val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); + val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); + writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); + } else { + its_configure_sgi(d, true); + } + + return 0; +} + +static int its_sgi_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); + void __iomem *base = gic_data_rdist_cpu(vpe->col_idx)->rd_base + SZ_128K; + u32 count = 1000000; /* 1s! */ + u32 status; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); + do { + status = readl_relaxed(base + GICR_VSGIPENDR); + if (!(status & GICR_VSGIPENDR_BUSY)) + goto out; + + count--; + if (!count) { + pr_err_ratelimited("Unable to get SGI status\n"); + goto out; + } + cpu_relax(); + udelay(1); + } while(count); + +out: + *val = !!(status & (1 << d->hwirq)); + + return 0; +} + static struct irq_chip its_sgi_irq_chip = { .name = "GICv4.1-sgi", .irq_mask = its_sgi_mask_irq, .irq_unmask = its_sgi_unmask_irq, .irq_set_affinity = its_sgi_set_affinity, + .irq_set_irqchip_state = its_sgi_set_irqchip_state, + .irq_get_irqchip_state = its_sgi_get_irqchip_state, }; static int its_sgi_irq_domain_alloc(struct irq_domain *domain, diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c73176d3ab2b..cb8563554ed2 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -340,6 +340,15 @@ #define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58) #define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0) +#define GICR_VSGIR 0x0080 + +#define GICR_VSGIR_VPEID GENMASK(15, 0) + +#define GICR_VSGIPENDR 0x0088 + +#define GICR_VSGIPENDR_BUSY (1U << 31) +#define GICR_VSGIPENDR_PENDING GENMASK(15, 0) + /* * ITS registers, offsets from ITS_base */ @@ -363,6 +372,11 @@ #define GITS_TRANSLATER 0x10040 +#define GITS_SGIR 0x20020 + +#define GITS_SGIR_VPEID GENMASK_ULL(47, 32) +#define GITS_SGIR_VINTID GENMASK_ULL(7, 0) + #define GITS_CTLR_ENABLE (1U << 0) #define GITS_CTLR_ImDe (1U << 1) #define GITS_CTLR_ITS_NUMBER_SHIFT 4 -- 2.20.1