linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Anup Patel <anup@brainfault.org>
Subject: [PATCH 09/12] riscv: clear the instruction cache and all registers when booting
Date: Mon, 28 Oct 2019 13:10:40 +0100	[thread overview]
Message-ID: <20191028121043.22934-10-hch@lst.de> (raw)
In-Reply-To: <20191028121043.22934-1-hch@lst.de>

When we get booted we want a clear slate without any leaks from previous
supervisors or the firmware.  Flush the instruction cache and then clear
all registers to known good values.  This is really important for the
upcoming nommu support that runs on M-mode, but can't really harm when
running in S-mode either.  Vaguely based on the concepts from opensbi.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/csr.h |  1 +
 arch/riscv/kernel/head.S     | 88 +++++++++++++++++++++++++++++++++++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 318192c66fd8..0a62d2d68455 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -92,6 +92,7 @@
 #define CSR_SATP		0x180
 
 #define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
 #define CSR_MIE			0x304
 #define CSR_MTVEC		0x305
 #define CSR_MSCRATCH		0x340
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fc9973086946..64eb8beb228e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -11,6 +11,7 @@
 #include <asm/thread_info.h>
 #include <asm/page.h>
 #include <asm/csr.h>
+#include <asm/hwcap.h>
 #include <asm/image.h>
 
 __INIT
@@ -51,12 +52,18 @@ _start_kernel:
 	csrw CSR_IP, zero
 
 #ifdef CONFIG_RISCV_M_MODE
+	/* flush the instruction cache */
+	fence.i
+
+	/* Reset all registers except ra, a0, a1 */
+	call reset_regs
+
 	/*
 	 * The hartid in a0 is expected later on, and we have no firmware
 	 * to hand it to us.
 	 */
 	csrr a0, CSR_MHARTID
-#endif
+#endif /* CONFIG_RISCV_M_MODE */
 
 	/* Load the global pointer */
 .option push
@@ -203,6 +210,85 @@ relocate:
 	j .Lsecondary_park
 END(_start)
 
+#ifdef CONFIG_RISCV_M_MODE
+ENTRY(reset_regs)
+	li	sp, 0
+	li	gp, 0
+	li	tp, 0
+	li	t0, 0
+	li	t1, 0
+	li	t2, 0
+	li	s0, 0
+	li	s1, 0
+	li	a2, 0
+	li	a3, 0
+	li	a4, 0
+	li	a5, 0
+	li	a6, 0
+	li	a7, 0
+	li	s2, 0
+	li	s3, 0
+	li	s4, 0
+	li	s5, 0
+	li	s6, 0
+	li	s7, 0
+	li	s8, 0
+	li	s9, 0
+	li	s10, 0
+	li	s11, 0
+	li	t3, 0
+	li	t4, 0
+	li	t5, 0
+	li	t6, 0
+	csrw	sscratch, 0
+
+#ifdef CONFIG_FPU
+	csrr	t0, CSR_MISA
+	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
+	bnez	t0, .Lreset_regs_done
+
+	li	t1, SR_FS
+	csrs	CSR_STATUS, t1
+	fmv.s.x	f0, zero
+	fmv.s.x	f1, zero
+	fmv.s.x	f2, zero
+	fmv.s.x	f3, zero
+	fmv.s.x	f4, zero
+	fmv.s.x	f5, zero
+	fmv.s.x	f6, zero
+	fmv.s.x	f7, zero
+	fmv.s.x	f8, zero
+	fmv.s.x	f9, zero
+	fmv.s.x	f10, zero
+	fmv.s.x	f11, zero
+	fmv.s.x	f12, zero
+	fmv.s.x	f13, zero
+	fmv.s.x	f14, zero
+	fmv.s.x	f15, zero
+	fmv.s.x	f16, zero
+	fmv.s.x	f17, zero
+	fmv.s.x	f18, zero
+	fmv.s.x	f19, zero
+	fmv.s.x	f20, zero
+	fmv.s.x	f21, zero
+	fmv.s.x	f22, zero
+	fmv.s.x	f23, zero
+	fmv.s.x	f24, zero
+	fmv.s.x	f25, zero
+	fmv.s.x	f26, zero
+	fmv.s.x	f27, zero
+	fmv.s.x	f28, zero
+	fmv.s.x	f29, zero
+	fmv.s.x	f30, zero
+	fmv.s.x	f31, zero
+	csrw	fcsr, 0
+	/* note that the caller must clear SR_FS */
+#endif /* CONFIG_FPU */
+.Lreset_regs_done:
+	ret
+END(reset_regs)
+#endif /* CONFIG_RISCV_M_MODE */
+
 __PAGE_ALIGNED_BSS
 	/* Empty zero page */
 	.balign PAGE_SIZE
-- 
2.20.1


  parent reply	other threads:[~2019-10-28 12:11 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 12:10 RISC-V nommu support v6 Christoph Hellwig
2019-10-28 12:10 ` [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-11-05 17:56   ` Paul Walmsley
2019-11-05 17:57   ` Paul Walmsley
2019-11-05 18:02     ` Marc Zyngier
2019-11-12 10:38   ` Thomas Gleixner
2019-11-14  7:30   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 02/12] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-11-14  7:31   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 03/12] riscv: poison SBI calls " Christoph Hellwig
2019-10-31 23:55   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 04/12] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-31 20:49   ` Paul Walmsley
2019-10-31 23:56   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 05/12] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-31 23:57   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 06/12] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-11-05 18:01   ` Paul Walmsley
2019-11-12 10:39   ` Thomas Gleixner
2019-11-17 23:06   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 07/12] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-28 12:10 ` [PATCH 08/12] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-28 12:10 ` Christoph Hellwig [this message]
2019-11-14  7:45   ` [PATCH 09/12] riscv: clear the instruction cache and all registers when booting Paul Walmsley
2019-10-28 12:10 ` [PATCH 10/12] riscv: add nommu support Christoph Hellwig
2019-11-17 23:13   ` Paul Walmsley
2019-12-16 22:03     ` David Abdurachmanov
2019-12-17  3:18       ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 11/12] riscv: provide a flat image loader Christoph Hellwig
2019-11-17 23:14   ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-30 20:21 ` RISC-V nommu support v6 Paul Walmsley
2019-10-31 15:52   ` Christoph Hellwig
2019-10-31 20:13     ` Paul Walmsley
2019-11-23  2:19     ` Paul Walmsley
2019-12-11  8:42       ` Greentime Hu
2020-02-12 12:19       ` Greentime Hu
2019-11-11  9:47   ` Christoph Hellwig
2019-11-11 17:02     ` Paul Walmsley
2019-11-13 13:18       ` Christoph Hellwig

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191028121043.22934-10-hch@lst.de \
    --to=hch@lst.de \
    --cc=anup@brainfault.org \
    --cc=damien.lemoal@wdc.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@sifive.com \
    --cc=paul.walmsley@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).