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Tue, 29 Oct 2019 11:17:06 +0000 From: To: , , , CC: , , Subject: [PATCH v3 11/32] mtd: spi-nor: Drop redundant error reports in Reg Ops callers Thread-Topic: [PATCH v3 11/32] mtd: spi-nor: Drop redundant error reports in Reg Ops callers Thread-Index: AQHVjkplMcJSJ7ucD0m8Dk/rmpqoYw== Date: Tue, 29 Oct 2019 11:17:05 +0000 Message-ID: <20191029111615.3706-12-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1fb8980d-adab-48b3-35e8-08d75c6187cf x-ms-traffictypediagnostic: MN2PR11MB3823: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4941; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1fb8980d-adab-48b3-35e8-08d75c6187cf X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:17:05.8340 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 39N0mRMXpldaXhZ4NrSklzUOo3Mv1cBElqcx8mCcxwIKuANIfu6spwbvvx113OrW8E52Xbmq3AbcsEn1V631VS83Wl5jVSY6iwVuDr21Lj4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3823 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 50 +++++++++------------------------------= ---- 1 file changed, 10 insertions(+), 40 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ec179eac2069..4a1ecf452a39 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -812,14 +812,7 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, u8= *sr_cr) return -EINVAL; } =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) { - dev_err(nor->dev, - "timeout while writing configuration register\n"); - return ret; - } - - return 0; + return spi_nor_wait_till_ready(nor); } =20 /* Write status register and ensure bits in mask match written values */ @@ -1853,10 +1846,8 @@ static int spansion_no_read_cr_quad_enable(struct sp= i_nor *nor) =20 /* Keep the current value of the Status Register. */ ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) { - dev_err(nor->dev, "error while reading status register\n"); + if (ret) return ret; - } =20 sr_cr[1] =3D CR_QUAD_EN_SPAN; =20 @@ -1878,16 +1869,13 @@ static int spansion_no_read_cr_quad_enable(struct s= pi_nor *nor) */ static int spansion_read_cr_quad_enable(struct spi_nor *nor) { - struct device *dev =3D nor->dev; u8 *sr_cr =3D nor->bouncebuf; int ret; =20 /* Check current Quad Enable bit value. */ ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) { - dev_err(dev, "error while reading configuration register\n"); + if (ret) return ret; - } =20 if (sr_cr[1] & CR_QUAD_EN_SPAN) return 0; @@ -1896,10 +1884,8 @@ static int spansion_read_cr_quad_enable(struct spi_n= or *nor) =20 /* Keep the current value of the Status Register. */ ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) { - dev_err(dev, "error while reading status register\n"); + if (ret) return ret; - } =20 ret =3D spi_nor_write_sr_cr(nor, sr_cr); if (ret) @@ -1954,10 +1940,8 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) } =20 ret =3D spi_nor_wait_till_ready(nor); - if (ret) { - dev_err(nor->dev, "timeout while writing status register 2\n"); + if (ret) return ret; - } =20 /* Read back and check it. */ ret =3D spi_nor_read_sr2(nor, sr2); @@ -1987,10 +1971,8 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) u8 mask =3D SR_BP2 | SR_BP1 | SR_BP0; =20 ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); - if (ret) { - dev_err(nor->dev, "error while reading status register\n"); + if (ret) return ret; - } =20 spi_nor_write_enable(nor); =20 @@ -2000,10 +1982,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) return ret; } =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - dev_err(nor->dev, "timeout while writing status register\n"); - return ret; + return spi_nor_wait_till_ready(nor); } =20 /** @@ -2027,11 +2006,8 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_n= or *nor) =20 /* Check current Quad Enable bit value. */ ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) { - dev_err(nor->dev, - "error while reading configuration register\n"); + if (ret) return ret; - } =20 /* * When the configuration register Quad Enable bit is one, only the @@ -2039,18 +2015,12 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_= nor *nor) */ if (sr_cr[1] & CR_QUAD_EN_SPAN) { ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) { - dev_err(nor->dev, - "error while reading status register\n"); + if (ret) return ret; - } =20 sr_cr[0] &=3D ~mask; =20 - ret =3D spi_nor_write_sr_cr(nor, sr_cr); - if (ret) - dev_err(nor->dev, "16-bit write register failed\n"); - return ret; + return spi_nor_write_sr_cr(nor, sr_cr); } =20 /* --=20 2.9.5