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Tue, 29 Oct 2019 11:17:12 +0000 From: To: , , , CC: , , Subject: [PATCH v3 15/32] mtd: spi-nor: Check for errors after each Register Operation Thread-Topic: [PATCH v3 15/32] mtd: spi-nor: Check for errors after each Register Operation Thread-Index: AQHVjkppKS3wm6HFREK56+6iD+phXA== Date: Tue, 29 Oct 2019 11:17:12 +0000 Message-ID: <20191029111615.3706-16-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 128fcbb6-f510-4dcc-dc7f-08d75c618bbd x-ms-traffictypediagnostic: MN2PR11MB3712: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 128fcbb6-f510-4dcc-dc7f-08d75c618bbd X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:17:12.3932 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wMGVy/5jtDP53L/JHzDGjW4lJeFC4U5ktpRMhfwPGu9rwfSbk6hfyIiByifRJIBcQkOWdTKmhA7Fw0Mj1zsIKDrHyL66rryI6EbdB9dRC/o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3712 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 81 ++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 60 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 889fd77dbe96..21f01fdcfa16 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -595,11 +595,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, b= ool enable) { int ret; =20 - spi_nor_write_enable(nor); + ret =3D=3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D macronix_set_4byte(nor, enable); - spi_nor_write_disable(nor); + if (ret) + return ret; =20 - return ret; + return spi_nor_write_disable(nor); } =20 static int spansion_set_4byte(struct spi_nor *nor, bool enable) @@ -665,11 +669,15 @@ static int winbond_set_4byte(struct spi_nor *nor, boo= l enable) * Register to be set to 1, so all 3-byte-address reads come from the * second 16M. We must clear the register to enable normal behavior. */ - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D spi_nor_write_ear(nor, 0); - spi_nor_write_disable(nor); + if (ret) + return ret; =20 - return ret; + return spi_nor_write_disable(nor); } =20 static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) @@ -855,7 +863,9 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, u8 = *sr_cr) { int ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 if (nor->spimem) { struct spi_mem_op op =3D @@ -885,7 +895,10 @@ static int spi_nor_write_sr_and_check(struct spi_nor *= nor, u8 status_new, { int ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D spi_nor_write_sr(nor, status_new); if (ret) return ret; @@ -1393,7 +1406,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor= *nor, u64 addr, u32 len) list_for_each_entry_safe(cmd, next, &erase_list, list) { nor->erase_opcode =3D cmd->opcode; while (cmd->count) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto destroy_erase_cmd_list; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1448,7 +1463,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) if (len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 ret =3D spi_nor_erase_chip(nor); if (ret) @@ -1475,7 +1492,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) /* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { while (len) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1496,7 +1515,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) goto erase_err; } =20 - spi_nor_write_disable(nor); + ret =3D spi_nor_write_disable(nor); =20 erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); @@ -1845,9 +1864,13 @@ static int macronix_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 - spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + if (ret) + return ret; =20 ret =3D spi_nor_wait_till_ready(nor); if (ret) @@ -2018,7 +2041,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D spi_nor_write_sr2(nor, sr2); if (ret) @@ -2059,7 +2084,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); if (ret) @@ -2676,7 +2703,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to,= size_t len, if (ret) return ret; =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; =20 nor->sst_write_second =3D false; =20 @@ -2714,14 +2743,19 @@ static int sst_write(struct mtd_info *mtd, loff_t t= o, size_t len, } nor->sst_write_second =3D false; =20 - spi_nor_write_disable(nor); + ret =3D spi_nor_write_disable(nor); + if (ret) + goto sst_write_err; + ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; =20 /* Write out trailing byte if it exists. */ if (actual !=3D len) { - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; =20 nor->program_opcode =3D SPINOR_OP_BP; ret =3D spi_nor_write_data(nor, to, 1, buf + actual); @@ -2731,8 +2765,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to= , size_t len, ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; - spi_nor_write_disable(nor); + actual +=3D 1; + + ret =3D spi_nor_write_disable(nor); } sst_write_err: *retlen +=3D actual; @@ -2783,7 +2819,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_= t to, size_t len, =20 addr =3D spi_nor_convert_addr(nor, addr); =20 - spi_nor_write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto write_err; + ret =3D spi_nor_write_data(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; --=20 2.9.5