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Tue, 29 Oct 2019 11:16:49 +0000 From: To: , , , CC: , , Subject: [PATCH v3 01/32] mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods Thread-Topic: [PATCH v3 01/32] mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods Thread-Index: AQHVjkpbEAWn0W/WNUW6ZfmVSIdQEA== Date: Tue, 29 Oct 2019 11:16:49 +0000 Message-ID: <20191029111615.3706-2-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3c880d6e-8d55-49f6-f867-08d75c617de8 x-ms-traffictypediagnostic: MN2PR11MB3712: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3c880d6e-8d55-49f6-f867-08d75c617de8 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:16:49.2226 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: BSbyhDV45DNBeW+yrUiCI0aXtzHozFl2pBbDB7qIVHTOwp5CwahaYkexUukJPeI9dzlYHVENqMFOJdGr1mjaOJax3VHEbPybuHJVmhLUF4I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3712 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 110 +++++++++++++++++++++-----------------= ---- 1 file changed, 56 insertions(+), 54 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index a6f9f833c862..aca8245fb6c4 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -393,7 +393,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, = loff_t to, size_t len, * Return the status register value. * Returns negative if error occurred. */ -static int read_sr(struct spi_nor *nor) +static int spi_nor_read_sr(struct spi_nor *nor) { int ret; =20 @@ -423,7 +423,7 @@ static int read_sr(struct spi_nor *nor) * Return the status register value. * Returns negative if error occurred. */ -static int read_fsr(struct spi_nor *nor) +static int spi_nor_read_fsr(struct spi_nor *nor) { int ret; =20 @@ -453,7 +453,7 @@ static int read_fsr(struct spi_nor *nor) * location. Return the configuration register value. * Returns negative if error occurred. */ -static int read_cr(struct spi_nor *nor) +static int spi_nor_read_cr(struct spi_nor *nor) { int ret; =20 @@ -482,7 +482,7 @@ static int read_cr(struct spi_nor *nor) * Write status register 1 byte * Returns negative if error occurred. */ -static int write_sr(struct spi_nor *nor, u8 val) +static int spi_nor_write_sr(struct spi_nor *nor, u8 val) { nor->bouncebuf[0] =3D val; if (nor->spimem) { @@ -503,7 +503,7 @@ static int write_sr(struct spi_nor *nor, u8 val) * Set write enable latch with Write Enable command. * Returns negative if error occurred. */ -static int write_enable(struct spi_nor *nor) +static int spi_nor_write_enable(struct spi_nor *nor) { if (nor->spimem) { struct spi_mem_op op =3D @@ -521,7 +521,7 @@ static int write_enable(struct spi_nor *nor) /* * Send write disable instruction to the chip. */ -static int write_disable(struct spi_nor *nor) +static int spi_nor_write_disable(struct spi_nor *nor) { if (nor->spimem) { struct spi_mem_op op =3D @@ -644,9 +644,9 @@ static int st_micron_set_4byte(struct spi_nor *nor, boo= l enable) { int ret; =20 - write_enable(nor); + spi_nor_write_enable(nor); ret =3D macronix_set_4byte(nor, enable); - write_disable(nor); + spi_nor_write_disable(nor); =20 return ret; } @@ -700,9 +700,9 @@ static int winbond_set_4byte(struct spi_nor *nor, bool = enable) * Register to be set to 1, so all 3-byte-address reads come from the * second 16M. We must clear the register to enable normal behavior. */ - write_enable(nor); + spi_nor_write_enable(nor); ret =3D spi_nor_write_ear(nor, 0); - write_disable(nor); + spi_nor_write_disable(nor); =20 return ret; } @@ -752,7 +752,7 @@ static int spi_nor_clear_sr(struct spi_nor *nor) =20 static int spi_nor_sr_ready(struct spi_nor *nor) { - int sr =3D read_sr(nor); + int sr =3D spi_nor_read_sr(nor); if (sr < 0) return sr; =20 @@ -786,7 +786,7 @@ static int spi_nor_clear_fsr(struct spi_nor *nor) =20 static int spi_nor_fsr_ready(struct spi_nor *nor) { - int fsr =3D read_fsr(nor); + int fsr =3D spi_nor_read_fsr(nor); if (fsr < 0) return fsr; =20 @@ -864,7 +864,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) * * Returns 0 if successful, non-zero otherwise. */ -static int erase_chip(struct spi_nor *nor) +static int spi_nor_erase_chip(struct spi_nor *nor) { dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); =20 @@ -1215,7 +1215,7 @@ static int spi_nor_erase_multi_sectors(struct spi_nor= *nor, u64 addr, u32 len) list_for_each_entry_safe(cmd, next, &erase_list, list) { nor->erase_opcode =3D cmd->opcode; while (cmd->count) { - write_enable(nor); + spi_nor_write_enable(nor); =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1270,9 +1270,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) if (len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout; =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 - if (erase_chip(nor)) { + if (spi_nor_erase_chip(nor)) { ret =3D -EIO; goto erase_err; } @@ -1298,7 +1298,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) /* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { while (len) { - write_enable(nor); + spi_nor_write_enable(nor); =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1319,7 +1319,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) goto erase_err; } =20 - write_disable(nor); + spi_nor_write_disable(nor); =20 erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); @@ -1328,12 +1328,13 @@ static int spi_nor_erase(struct mtd_info *mtd, stru= ct erase_info *instr) } =20 /* Write status register and ensure bits in mask match written values */ -static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) +static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new, + u8 mask) { int ret; =20 - write_enable(nor); - ret =3D write_sr(nor, status_new); + spi_nor_write_enable(nor); + ret =3D spi_nor_write_sr(nor, status_new); if (ret) return ret; =20 @@ -1341,7 +1342,7 @@ static int write_sr_and_check(struct spi_nor *nor, u8= status_new, u8 mask) if (ret) return ret; =20 - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (ret < 0) return ret; =20 @@ -1447,7 +1448,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, = uint64_t len) bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB= ; bool use_top; =20 - status_old =3D read_sr(nor); + status_old =3D spi_nor_read_sr(nor); if (status_old < 0) return status_old; =20 @@ -1509,7 +1510,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, = uint64_t len) if ((status_new & mask) < (status_old & mask)) return -EINVAL; =20 - return write_sr_and_check(nor, status_new, mask); + return spi_nor_write_sr_and_check(nor, status_new, mask); } =20 /* @@ -1527,7 +1528,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs= , uint64_t len) bool can_be_top =3D true, can_be_bottom =3D nor->flags & SNOR_F_HAS_SR_TB= ; bool use_top; =20 - status_old =3D read_sr(nor); + status_old =3D spi_nor_read_sr(nor); if (status_old < 0) return status_old; =20 @@ -1592,7 +1593,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs= , uint64_t len) if ((status_new & mask) > (status_old & mask)) return -EINVAL; =20 - return write_sr_and_check(nor, status_new, mask); + return spi_nor_write_sr_and_check(nor, status_new, mask); } =20 /* @@ -1606,7 +1607,7 @@ static int stm_is_locked(struct spi_nor *nor, loff_t = ofs, uint64_t len) { int status; =20 - status =3D read_sr(nor); + status =3D spi_nor_read_sr(nor); if (status < 0) return status; =20 @@ -1670,11 +1671,11 @@ static int spi_nor_is_locked(struct mtd_info *mtd, = loff_t ofs, uint64_t len) * second byte will be written to the configuration register. * Return negative if error occurred. */ -static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) +static int spi_nor_write_sr_cr(struct spi_nor *nor, u8 *sr_cr) { int ret; =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 if (nor->spimem) { struct spi_mem_op op =3D @@ -1719,21 +1720,21 @@ static int macronix_quad_enable(struct spi_nor *nor= ) { int ret, val; =20 - val =3D read_sr(nor); + val =3D spi_nor_read_sr(nor); if (val < 0) return val; if (val & SR_QUAD_EN_MX) return 0; =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 - write_sr(nor, val | SR_QUAD_EN_MX); + spi_nor_write_sr(nor, val | SR_QUAD_EN_MX); =20 ret =3D spi_nor_wait_till_ready(nor); if (ret) return ret; =20 - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { dev_err(nor->dev, "Macronix Quad bit not set\n"); return -EINVAL; @@ -1758,7 +1759,8 @@ static int macronix_quad_enable(struct spi_nor *nor) * some very old and few memories don't support this instruction. If a pul= l-up * resistor is present on the MISO/IO1 line, we might still be able to pas= s the * "read back" test because the QSPI memory doesn't recognize the command, - * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0x= FF. + * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr() re= turns + * 0xFF. * * bit 1 of the Configuration Register is the QE bit for Spansion like QSP= I * memories. @@ -1772,12 +1774,12 @@ static int spansion_quad_enable(struct spi_nor *nor= ) =20 sr_cr[0] =3D 0; sr_cr[1] =3D CR_QUAD_EN_SPAN; - ret =3D write_sr_cr(nor, sr_cr); + ret =3D spi_nor_write_sr_cr(nor, sr_cr); if (ret) return ret; =20 /* read back and check it */ - ret =3D read_cr(nor); + ret =3D spi_nor_read_cr(nor); if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { dev_err(nor->dev, "Spansion Quad bit not set\n"); return -EINVAL; @@ -1805,7 +1807,7 @@ static int spansion_no_read_cr_quad_enable(struct spi= _nor *nor) int ret; =20 /* Keep the current value of the Status Register. */ - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading status register\n"); return -EINVAL; @@ -1813,7 +1815,7 @@ static int spansion_no_read_cr_quad_enable(struct spi= _nor *nor) sr_cr[0] =3D ret; sr_cr[1] =3D CR_QUAD_EN_SPAN; =20 - return write_sr_cr(nor, sr_cr); + return spi_nor_write_sr_cr(nor, sr_cr); } =20 /** @@ -1836,7 +1838,7 @@ static int spansion_read_cr_quad_enable(struct spi_no= r *nor) int ret; =20 /* Check current Quad Enable bit value. */ - ret =3D read_cr(nor); + ret =3D spi_nor_read_cr(nor); if (ret < 0) { dev_err(dev, "error while reading configuration register\n"); return -EINVAL; @@ -1848,19 +1850,19 @@ static int spansion_read_cr_quad_enable(struct spi_= nor *nor) sr_cr[1] =3D ret | CR_QUAD_EN_SPAN; =20 /* Keep the current value of the Status Register. */ - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(dev, "error while reading status register\n"); return -EINVAL; } sr_cr[0] =3D ret; =20 - ret =3D write_sr_cr(nor, sr_cr); + ret =3D spi_nor_write_sr_cr(nor, sr_cr); if (ret) return ret; =20 /* Read back and check it. */ - ret =3D read_cr(nor); + ret =3D spi_nor_read_cr(nor); if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { dev_err(nor->dev, "Spansion Quad bit not set\n"); return -EINVAL; @@ -1926,7 +1928,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 ret =3D spi_nor_write_sr2(nor, sr2); if (ret < 0) { @@ -1964,15 +1966,15 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) int ret; u8 mask =3D SR_BP2 | SR_BP1 | SR_BP0; =20 - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading status register\n"); return ret; } =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 - ret =3D write_sr(nor, ret & ~mask); + ret =3D spi_nor_write_sr(nor, ret & ~mask); if (ret) { dev_err(nor->dev, "write to status register failed\n"); return ret; @@ -2004,7 +2006,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) u8 *sr_cr =3D nor->bouncebuf; =20 /* Check current Quad Enable bit value. */ - ret =3D read_cr(nor); + ret =3D spi_nor_read_cr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading configuration register\n"); @@ -2018,7 +2020,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) if (ret & CR_QUAD_EN_SPAN) { sr_cr[1] =3D ret; =20 - ret =3D read_sr(nor); + ret =3D spi_nor_read_sr(nor); if (ret < 0) { dev_err(nor->dev, "error while reading status register\n"); @@ -2026,7 +2028,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) } sr_cr[0] =3D ret & ~mask; =20 - ret =3D write_sr_cr(nor, sr_cr); + ret =3D spi_nor_write_sr_cr(nor, sr_cr); if (ret) dev_err(nor->dev, "16-bit write register failed\n"); return ret; @@ -2602,7 +2604,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to,= size_t len, if (ret) return ret; =20 - write_enable(nor); + spi_nor_write_enable(nor); =20 nor->sst_write_second =3D false; =20 @@ -2641,14 +2643,14 @@ static int sst_write(struct mtd_info *mtd, loff_t t= o, size_t len, } nor->sst_write_second =3D false; =20 - write_disable(nor); + spi_nor_write_disable(nor); ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; =20 /* Write out trailing byte if it exists. */ if (actual !=3D len) { - write_enable(nor); + spi_nor_write_enable(nor); =20 nor->program_opcode =3D SPINOR_OP_BP; ret =3D spi_nor_write_data(nor, to, 1, buf + actual); @@ -2659,7 +2661,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to,= size_t len, ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; - write_disable(nor); + spi_nor_write_disable(nor); actual +=3D 1; } sst_write_err: @@ -2711,7 +2713,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t= to, size_t len, =20 addr =3D spi_nor_convert_addr(nor, addr); =20 - write_enable(nor); + spi_nor_write_enable(nor); ret =3D spi_nor_write_data(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; --=20 2.9.5