[PATCH] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core

[PATCH] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core

[Florian Fainelli]

From: Doug Berger <opendmb@gmail.com>

The Broadcom Brahma-B53 core is susceptible to the issue described by
ARM64_ERRATUM_845719 so this commit enables the workaround to be applied
when executing on that core.

Since there are now multiple entries to match, we must convert the
existing ARM64_ERRATUM_845719 into an erratum list.

Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm64/include/asm/cputype.h |  2 ++
 arch/arm64/kernel/cpu_errata.c   | 13 +++++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index b1454d117cd2..aca07c2f6e6e 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -79,6 +79,7 @@
 #define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3
 #define CAVIUM_CPU_PART_THUNDERX2	0x0AF
 
+#define BRCM_CPU_PART_BRAHMA_B53	0x100
 #define BRCM_CPU_PART_VULCAN		0x516
 
 #define QCOM_CPU_PART_FALKOR_V1		0x800
@@ -105,6 +106,7 @@
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
+#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6c3b10a41bd8..c065dd48d661 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -737,6 +737,16 @@ static const struct midr_range erratum_1418040_list[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_845719
+static const struct midr_range erratum_845719_list[] = {
+	/* Cortex-A53 r0p[01234] */
+	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+	/* Brahma-B53 r0p[0] */
+	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
+	{},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 	{
@@ -777,10 +787,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_845719
 	{
-	/* Cortex-A53 r0p[01234] */
 		.desc = "ARM erratum 845719",
 		.capability = ARM64_WORKAROUND_845719,
-		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
+		ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
 	},
 #endif
 #ifdef CONFIG_CAVIUM_ERRATUM_23154
-- 
2.17.1

Re: [PATCH] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core

[Will Deacon]

On Tue, Oct 29, 2019 at 12:16:19PM -0700, Florian Fainelli wrote:
> From: Doug Berger <opendmb@gmail.com>
> 
> The Broadcom Brahma-B53 core is susceptible to the issue described by
> ARM64_ERRATUM_845719 so this commit enables the workaround to be applied
> when executing on that core.
> 
> Since there are now multiple entries to match, we must convert the
> existing ARM64_ERRATUM_845719 into an erratum list.

Looks fine to me, but I have to ask: are you sure you don't want to select
any of ARM64_ERRATUM_{826319, 827319, 824069, 819472, 843419} ?

Also, please can you update Documentation/arm64/silicon-errata.rst ?

Will

Re: [PATCH] arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core

[Florian Fainelli]

On 10/31/19 6:21 AM, Will Deacon wrote:
> On Tue, Oct 29, 2019 at 12:16:19PM -0700, Florian Fainelli wrote:
>> From: Doug Berger <opendmb@gmail.com>
>>
>> The Broadcom Brahma-B53 core is susceptible to the issue described by
>> ARM64_ERRATUM_845719 so this commit enables the workaround to be applied
>> when executing on that core.
>>
>> Since there are now multiple entries to match, we must convert the
>> existing ARM64_ERRATUM_845719 into an erratum list.
> 
> Looks fine to me, but I have to ask: are you sure you don't want to select
> any of ARM64_ERRATUM_{826319, 827319, 824069, 819472, 843419} ?

Out of this list, we are only subject to 843419 (and 845719) since I am
told that only r0p4 (inclusive) and beyond are relevant.

Good thing that you mentioned 843419 because in our downstream kernel
(4.9) this is a "static" workaround in that once enabled, it just is
unconditionally active, whereas in later kernels there is some
additional run time determination of whether this is really needed, thanks!

> 
> Also, please can you update Documentation/arm64/silicon-errata.rst ?

Absolutely.
-- 
Florian