From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 388A5CA9ECF for ; Fri, 1 Nov 2019 12:44:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 054892067D for ; Fri, 1 Nov 2019 12:44:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk header.b="QVAzMQee" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730813AbfKAMok (ORCPT ); Fri, 1 Nov 2019 08:44:40 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:42996 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730306AbfKAMmV (ORCPT ); Fri, 1 Nov 2019 08:42:21 -0400 Received: by mail-lf1-f66.google.com with SMTP id z12so7134501lfj.9 for ; Fri, 01 Nov 2019 05:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rasmusvillemoes.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZekbabXCPgDix0mV9AcQnO633/TLQ+c6dMS4dOgnB5g=; b=QVAzMQeemMF6R6d7TTwAc3657T/pPexctuCtVwIwHVAqR2vAdUOiA2bfcLKLDTMjHA oVmJVURMFxEEXRlccrU7D+1Xmo/AuLuMSIOLP67Iy9H/PIqwyvs9U/KRIEpLIbeZkIl3 Gfevhkh+THITVXgc8HQK1Ct1LvsNFxW9vZwtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZekbabXCPgDix0mV9AcQnO633/TLQ+c6dMS4dOgnB5g=; b=ZFOAmDWjvuAhtFUay6M0NvfuOQyUGXdOHmgFEzU2WzKZBJ7OQMlhUdkc8awNiNG45/ Nni+flLRs2KgzMes7xfFCxWcBI/T6075+eqV3w1JaCpAXqWqsCFDn2NddeDaQy5yJsvV c84fGtvBcfKfJld+tU2cmM+0DjK+MkC+lGDChGDJvOYHHsSqeQQ6MjvJVzqYY/bvFAsk o478DC6enpbt7ea/Q7vC+YMy+XDZW/KAFJOUIOekQnrem8l8rhE+OhTfHcUGNfMRq13N 65tYTs6UQ3yfKorWkKPt2KNxRbi0EY2fj+egaReG8JtSXGz9dxH8/NJzn/pBhwTeKZXN wDJQ== X-Gm-Message-State: APjAAAWKOfIKAUUCXDURPBDZqzMZZTimcAxIHdMnSBF8eolCN0H93Lia luNKt+VDFQkT9wbFmnuUknY0Yg== X-Google-Smtp-Source: APXvYqz2jsMS9JYs9VxpkC5EaFPwpcxbu5+sLWNm+YlH1FIE8vsw0bPlxFMSoOxtBsrmo5/y3VzHFA== X-Received: by 2002:a05:6512:1de:: with SMTP id f30mr7177318lfp.176.1572612138393; Fri, 01 Nov 2019 05:42:18 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id o26sm2458540lfi.57.2019.11.01.05.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2019 05:42:17 -0700 (PDT) From: Rasmus Villemoes To: Qiang Zhao , Li Yang , Christophe Leroy Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Scott Wood , Rasmus Villemoes , netdev@vger.kernel.org Subject: [PATCH v3 03/36] soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers Date: Fri, 1 Nov 2019 13:41:37 +0100 Message-Id: <20191101124210.14510-4-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191101124210.14510-1-linux@rasmusvillemoes.dk> References: <20191018125234.21825-1-linux@rasmusvillemoes.dk> <20191101124210.14510-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make it clear that these operate on big-endian registers (i.e. use the iowrite*be primitives) before we introduce more uses of them and allow the QE drivers to be built for platforms other than ppc32. Signed-off-by: Rasmus Villemoes --- drivers/net/wan/fsl_ucc_hdlc.c | 4 ++-- drivers/soc/fsl/qe/ucc.c | 10 +++++----- include/soc/fsl/qe/qe.h | 18 +++++++++--------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c index ca0f3be2b6bf..ce6af7d5380f 100644 --- a/drivers/net/wan/fsl_ucc_hdlc.c +++ b/drivers/net/wan/fsl_ucc_hdlc.c @@ -623,8 +623,8 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget) if (howmany < budget) { napi_complete_done(napi, howmany); - qe_setbits32(priv->uccf->p_uccm, - (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16); + qe_setbits_be32(priv->uccf->p_uccm, + (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16); } return howmany; diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c index 024d239ac1e1..ae9f2cf560cb 100644 --- a/drivers/soc/fsl/qe/ucc.c +++ b/drivers/soc/fsl/qe/ucc.c @@ -540,8 +540,8 @@ int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : &qe_mux_reg->cmxsi1cr_h; - qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, - clock_bits << shift); + qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, + clock_bits << shift); return 0; } @@ -650,9 +650,9 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, shift = ucc_get_tdm_sync_shift(mode, tdm_num); - qe_clrsetbits32(&qe_mux_reg->cmxsi1syr, - QE_CMXUCR_TX_CLK_SRC_MASK << shift, - source << shift); + qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr, + QE_CMXUCR_TX_CLK_SRC_MASK << shift, + source << shift); return 0; } diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index c1036d16ed03..a1aa4eb28f0c 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -241,20 +241,20 @@ static inline int qe_alive_during_sleep(void) #define qe_muram_offset cpm_muram_offset #define qe_muram_dma cpm_muram_dma -#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) -#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) +#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) +#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) -#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) -#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) +#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) +#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) -#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) -#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) +#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) +#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) -#define qe_clrsetbits32(addr, clear, set) \ +#define qe_clrsetbits_be32(addr, clear, set) \ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) -#define qe_clrsetbits16(addr, clear, set) \ +#define qe_clrsetbits_be16(addr, clear, set) \ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) -#define qe_clrsetbits8(addr, clear, set) \ +#define qe_clrsetbits_8(addr, clear, set) \ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) /* Structure that defines QE firmware binary files. -- 2.23.0