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* [PATCH v3 0/7] Add support for H6 PWM
@ 2019-11-05 13:14 Clément Péron
  2019-11-05 13:14 ` [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron
                   ` (6 more replies)
  0 siblings, 7 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Clément Péron

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

I didn't add the acked-tags as there are big changes.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v3:
 - Documentation update to allow one clock without name
 - Change reset optional to shared
 - If reset probe failed return an error
 - Remove old clock probe
 - Update bypass enabled formula

Changes in v2:
 - Remove allOf in Documentation
 - Add H6 example in Documentation
 - Change clock name from "pwm" to "mod"
 - Change reset quirk to optional probe
 - Change bus_clock quirk to optional probe
 - Add limitation comment about mod_clk_output
 - Add quirk for mod_clk_output
 - Change bypass formula

Clément Péron (1):
  [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM

Jernej Skrabec (6):
  dt-bindings: pwm: allwinner: Add H6 PWM description
  pwm: sun4i: Add an optional probe for reset line
  pwm: sun4i: Add an optional probe for bus clock
  pwm: sun4i: Add support to output source clock directly
  pwm: sun4i: Add support for H6 PWM
  arm64: dts: allwinner: h6: Add PWM node

 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml |  47 +++++++
 .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |   4 +
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  10 ++
 drivers/pwm/pwm-sun4i.c                       | 125 +++++++++++++++++-
 4 files changed, 181 insertions(+), 5 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 21:33   ` Rob Herring
  2019-11-05 13:14 ` [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

H6 PWM block is basically the same as A20 PWM, except that it also has
bus clock and reset line which needs to be handled accordingly.

Expand Allwinner PWM binding with H6 PWM specifics.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 0ac52f83a58c..9fc32c1d94b4 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -30,13 +30,50 @@ properties:
       - items:
           - const: allwinner,sun50i-h5-pwm
           - const: allwinner,sun5i-a13-pwm
+      - const: allwinner,sun50i-h6-pwm
 
   reg:
     maxItems: 1
 
   clocks:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: Bus Clock
+      - description: Module Clock
+
+  # Even though it only applies to subschemas under the conditionals,
+  # not listing them here will trigger a warning because of the
+  # additionalsProperties set to false.
+  clock-names: true
+  resets:
     maxItems: 1
 
+  if:
+    properties:
+      compatible:
+        contains:
+          const: allwinner,sun50i-h6-pwm
+
+  then:
+    properties:
+      clocks:
+        minItems: 2
+
+      clock-names:
+        items:
+          - const: mod
+          - const: bus
+
+    required:
+      - clock-names
+      - resets
+
+  else:
+    properties:
+      clocks:
+        maxItems: 1
+
 required:
   - "#pwm-cells"
   - compatible
@@ -54,4 +91,14 @@ examples:
         #pwm-cells = <3>;
     };
 
+  - |
+    pwm@300a000 {
+      compatible = "allwinner,sun50i-h6-pwm";
+      reg = <0x0300a000 0x400>;
+      clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+      clock-names = "mod", "bus";
+      resets = <&ccu RST_BUS_PWM>;
+      #pwm-cells = <3>;
+    };
+
 ...
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
  2019-11-05 13:14 ` [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 13:36   ` Philipp Zabel
  2019-11-05 13:53   ` Uwe Kleine-König
  2019-11-05 13:14 ` [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock Clément Péron
                   ` (4 subsequent siblings)
  6 siblings, 2 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 6f5840a1a82d..9ba83769a478 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pwm.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/time.h>
@@ -78,6 +79,7 @@ struct sun4i_pwm_data {
 struct sun4i_pwm_chip {
 	struct pwm_chip chip;
 	struct clk *clk;
+	struct reset_control *rst;
 	void __iomem *base;
 	spinlock_t ctrl_lock;
 	const struct sun4i_pwm_data *data;
@@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 	if (IS_ERR(pwm->clk))
 		return PTR_ERR(pwm->clk);
 
+	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+	if (IS_ERR(pwm->rst)) {
+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "get reset failed %ld\n",
+				PTR_ERR(pwm->rst));
+		return PTR_ERR(pwm->rst);
+	}
+
+	/* Deassert reset */
+	ret = reset_control_deassert(pwm->rst);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot deassert reset control\n");
+		return ret;
+	}
+
 	pwm->chip.dev = &pdev->dev;
 	pwm->chip.ops = &sun4i_pwm_ops;
 	pwm->chip.base = -1;
@@ -377,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 	ret = pwmchip_add(&pwm->chip);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
-		return ret;
+		goto err_pwm_add;
 	}
 
 	platform_set_drvdata(pdev, pwm);
 
 	return 0;
+
+err_pwm_add:
+	reset_control_assert(pwm->rst);
+
+	return ret;
 }
 
 static int sun4i_pwm_remove(struct platform_device *pdev)
 {
 	struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = pwmchip_remove(&pwm->chip);
+	if (ret)
+		return ret;
+
+	reset_control_assert(pwm->rst);
 
-	return pwmchip_remove(&pwm->chip);
+	return 0;
 }
 
 static struct platform_driver sun4i_pwm_driver = {
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
  2019-11-05 13:14 ` [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron
  2019-11-05 13:14 ` [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 13:57   ` Uwe Kleine-König
  2019-11-05 13:14 ` [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly Clément Péron
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it and a fallback for previous
bindings without name on module clock.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 9ba83769a478..54e19fa56a4e 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {
 
 struct sun4i_pwm_chip {
 	struct pwm_chip chip;
+	struct clk *bus_clk;
 	struct clk *clk;
 	struct reset_control *rst;
 	void __iomem *base;
@@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 	if (IS_ERR(pwm->base))
 		return PTR_ERR(pwm->base);
 
-	pwm->clk = devm_clk_get(&pdev->dev, NULL);
-	if (IS_ERR(pwm->clk))
+	/* Get all clocks and reset line */
+	pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+	if (IS_ERR(pwm->clk)) {
+		dev_err(&pdev->dev, "get clock failed %ld\n",
+			PTR_ERR(pwm->clk));
 		return PTR_ERR(pwm->clk);
+	}
+
+	/*
+	 * Fallback for old dtbs with a single clock and no name.
+	 * If a parent has a clock-name called "mod" whereas the
+	 * current node is unnamed the clock reference will be
+	 * incorrectly obtained and will not go into this fallback.
+	 */
+	if (!pwm->clk) {
+		pwm->clk = devm_clk_get(&pdev->dev, NULL);
+		if (IS_ERR(pwm->clk)) {
+			dev_err(&pdev->dev, "get clock failed %ld\n",
+				PTR_ERR(pwm->clk));
+			return PTR_ERR(pwm->clk);
+		}
+	}
+
+	pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+	if (IS_ERR(pwm->bus_clk)) {
+		dev_err(&pdev->dev, "get bus_clock failed %ld\n",
+			PTR_ERR(pwm->bus_clk));
+		return PTR_ERR(pwm->bus_clk);
+	}
 
 	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 	if (IS_ERR(pwm->rst)) {
@@ -382,6 +409,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/*
+	 * We're keeping the bus clock on for the sake of simplicity.
+	 * Actually it only needs to be on for hardware register
+	 * accesses.
+	 */
+	ret = clk_prepare_enable(pwm->bus_clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
+		goto err_bus;
+	}
+
 	pwm->chip.dev = &pdev->dev;
 	pwm->chip.ops = &sun4i_pwm_ops;
 	pwm->chip.base = -1;
@@ -402,6 +440,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
 	return 0;
 
 err_pwm_add:
+	clk_disable_unprepare(pwm->bus_clk);
+err_bus:
 	reset_control_assert(pwm->rst);
 
 	return ret;
@@ -416,6 +456,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	clk_disable_unprepare(pwm->bus_clk);
 	reset_control_assert(pwm->rst);
 
 	return 0;
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
                   ` (2 preceding siblings ...)
  2019-11-05 13:14 ` [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 14:56   ` Uwe Kleine-König
  2019-11-05 13:14 ` [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM Clément Péron
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 54e19fa56a4e..810abf47c261 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -3,6 +3,10 @@
  * Driver for Allwinner sun4i Pulse Width Modulation Controller
  *
  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ *   and the currently running period is not guaranteed to be completed
  */
 
 #include <linux/bitops.h>
@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
 
 struct sun4i_pwm_data {
 	bool has_prescaler_bypass;
+	bool has_direct_mod_clk_output;
 	unsigned int npwm;
 };
 
@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 
 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 
+	/*
+	 * PWM chapter in H6 manual has a diagram which explains that if bypass
+	 * bit is set, no other setting has any meaning. Even more, experiment
+	 * proved that also enable bit is ignored in this case.
+	 */
+	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+	    sun4i_pwm->data->has_direct_mod_clk_output) {
+		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+		state->duty_cycle = state->period / 2;
+		state->polarity = PWM_POLARITY_NORMAL;
+		state->enabled = true;
+		return;
+	}
+
 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
 	    sun4i_pwm->data->has_prescaler_bypass)
 		prescaler = 1;
@@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 {
 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 	struct pwm_state cstate;
-	u32 ctrl;
+	u32 ctrl, clk_rate;
+	bool bypass;
 	int ret;
 	unsigned int delay_us;
 	unsigned long now;
@@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 		}
 	}
 
+	/*
+	 * Although it would make much more sense to check for bypass in
+	 * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
+	 */
+	clk_rate = clk_get_rate(sun4i_pwm->clk);
+	bypass = state->enabled &&
+		 (state->period * clk_rate >= NSEC_PER_SEC) &&
+		 (state->duty_cycle * 2 == state->period);
+
 	spin_lock(&sun4i_pwm->ctrl_lock);
 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 
@@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 	}
 
+	if (sun4i_pwm->data->has_direct_mod_clk_output) {
+		if (bypass)
+			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+		else
+			ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+	}
+
 	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 
 	spin_unlock(&sun4i_pwm->ctrl_lock);
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
                   ` (3 preceding siblings ...)
  2019-11-05 13:14 ` [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 14:57   ` Uwe Kleine-König
  2019-11-05 13:14 ` [PATCH v3 6/7] arm64: dts: allwinner: h6: Add PWM node Clément Péron
  2019-11-05 13:14 ` [PATCH v3 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Clément Péron
  6 siblings, 1 reply; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 drivers/pwm/pwm-sun4i.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 810abf47c261..e257c1b1fc67 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -359,6 +359,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
 	.npwm = 1,
 };
 
+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
+	.has_prescaler_bypass = true,
+	.has_direct_mod_clk_output = true,
+	.npwm = 2,
+};
+
 static const struct of_device_id sun4i_pwm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun4i-a10-pwm",
@@ -375,6 +381,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
 	}, {
 		.compatible = "allwinner,sun8i-h3-pwm",
 		.data = &sun4i_pwm_single_bypass,
+	}, {
+		.compatible = "allwinner,sun50i-h6-pwm",
+		.data = &sun50i_h6_pwm_data,
 	}, {
 		/* sentinel */
 	},
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 6/7] arm64: dts: allwinner: h6: Add PWM node
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
                   ` (4 preceding siblings ...)
  2019-11-05 13:14 ` [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  2019-11-05 13:14 ` [PATCH v3 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Clément Péron
  6 siblings, 0 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec, Clément Péron

From: Jernej Skrabec <jernej.skrabec@siol.net>

Allwinner H6 PWM is similar to that in A20 except that it has additional
bus clock and reset line.

Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 0d5ea19336a1..b0d9ee1ead13 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -222,6 +222,16 @@
 			status = "disabled";
 		};
 
+		pwm: pwm@300a000 {
+			compatible = "allwinner,sun50i-h6-pwm";
+			reg = <0x0300a000 0x400>;
+			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+			clock-names = "mod", "bus";
+			resets = <&ccu RST_BUS_PWM>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		pio: pinctrl@300b000 {
 			compatible = "allwinner,sun50i-h6-pinctrl";
 			reg = <0x0300b000 0x400>;
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v3 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM
  2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
                   ` (5 preceding siblings ...)
  2019-11-05 13:14 ` [PATCH v3 6/7] arm64: dts: allwinner: h6: Add PWM node Clément Péron
@ 2019-11-05 13:14 ` Clément Péron
  6 siblings, 0 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 13:14 UTC (permalink / raw)
  To: Thierry Reding, 'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Clément Péron

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 1d05d570142f..38aba7e5bbd9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -131,6 +131,10 @@
 	vcc-pg-supply = <&reg_aldo1>;
 };
 
+&pwm {
+	status = "okay";
+};
+
 &r_i2c {
 	status = "okay";
 
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line
  2019-11-05 13:14 ` [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron
@ 2019-11-05 13:36   ` Philipp Zabel
  2019-11-05 14:01     ` Clément Péron
  2019-11-05 13:53   ` Uwe Kleine-König
  1 sibling, 1 reply; 19+ messages in thread
From: Philipp Zabel @ 2019-11-05 13:36 UTC (permalink / raw)
  To: Clément Péron, Thierry Reding,
	'Uwe Kleine-König',
	Rob Herring, Mark Rutland, Maxime Ripard, Chen-Yu Tsai,
	Philipp Zabel
  Cc: linux-pwm, devicetree, linux-arm-kernel, linux-kernel, Jernej Skrabec

On Tue, 2019-11-05 at 14:14 +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> H6 PWM core needs deasserted reset line in order to work.
> 
> Add an optional probe for it.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

> ---
>  drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 6f5840a1a82d..9ba83769a478 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
[...]
> @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
>  	if (IS_ERR(pwm->clk))
>  		return PTR_ERR(pwm->clk);
>  
> +	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
> +	if (IS_ERR(pwm->rst)) {
> +		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> +			dev_err(&pdev->dev, "get reset failed %ld\n",
> +				PTR_ERR(pwm->rst));
> +		return PTR_ERR(pwm->rst);
> +	}
> +
> +	/* Deassert reset */

Nitpick: isn't the API function name explanatory enough?

regards
Philipp


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line
  2019-11-05 13:14 ` [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron
  2019-11-05 13:36   ` Philipp Zabel
@ 2019-11-05 13:53   ` Uwe Kleine-König
  1 sibling, 0 replies; 19+ messages in thread
From: Uwe Kleine-König @ 2019-11-05 13:53 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

On Tue, Nov 05, 2019 at 02:14:51PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> H6 PWM core needs deasserted reset line in order to work.
> 
> Add an optional probe for it.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock
  2019-11-05 13:14 ` [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock Clément Péron
@ 2019-11-05 13:57   ` Uwe Kleine-König
  2019-11-05 14:06     ` Clément Péron
  0 siblings, 1 reply; 19+ messages in thread
From: Uwe Kleine-König @ 2019-11-05 13:57 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

On Tue, Nov 05, 2019 at 02:14:52PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> H6 PWM core needs bus clock to be enabled in order to work.
> 
> Add an optional probe for it and a fallback for previous
> bindings without name on module clock.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 9ba83769a478..54e19fa56a4e 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -78,6 +78,7 @@ struct sun4i_pwm_data {
>  
>  struct sun4i_pwm_chip {
>  	struct pwm_chip chip;
> +	struct clk *bus_clk;
>  	struct clk *clk;
>  	struct reset_control *rst;
>  	void __iomem *base;
> @@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
>  	if (IS_ERR(pwm->base))
>  		return PTR_ERR(pwm->base);
>  
> -	pwm->clk = devm_clk_get(&pdev->dev, NULL);
> -	if (IS_ERR(pwm->clk))
> +	/* Get all clocks and reset line */
> +	pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
> +	if (IS_ERR(pwm->clk)) {
> +		dev_err(&pdev->dev, "get clock failed %ld\n",
> +			PTR_ERR(pwm->clk));

Please only print this message if PTR_ERR(pwm->clk) != -EPROBE_DEFER.
You might also want to make use of commit 57f5677e535b ("printf: add
support for printing symbolic error names") and use

	dev_err(&pdev->dev, "get clock failed: %pe\n", pwm->clk);

Other than that the patch is fine for me.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line
  2019-11-05 13:36   ` Philipp Zabel
@ 2019-11-05 14:01     ` Clément Péron
  0 siblings, 0 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 14:01 UTC (permalink / raw)
  To: Philipp Zabel
  Cc: Thierry Reding, Uwe Kleine-König, Rob Herring, Mark Rutland,
	Maxime Ripard, Chen-Yu Tsai, Philipp Zabel, linux-pwm,
	devicetree, linux-arm-kernel, linux-kernel, Jernej Skrabec

Hi Philipp,

On Tue, 5 Nov 2019 at 14:36, Philipp Zabel <p.zabel@pengutronix.de> wrote:
>
> On Tue, 2019-11-05 at 14:14 +0100, Clément Péron wrote:
> > From: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > H6 PWM core needs deasserted reset line in order to work.
> >
> > Add an optional probe for it.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
>
> > ---
> >  drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
> >  1 file changed, 31 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index 6f5840a1a82d..9ba83769a478 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> [...]
> > @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
> >       if (IS_ERR(pwm->clk))
> >               return PTR_ERR(pwm->clk);
> >
> > +     pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
> > +     if (IS_ERR(pwm->rst)) {
> > +             if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> > +                     dev_err(&pdev->dev, "get reset failed %ld\n",
> > +                             PTR_ERR(pwm->rst));
> > +             return PTR_ERR(pwm->rst);
> > +     }
> > +
> > +     /* Deassert reset */
>
> Nitpick: isn't the API function name explanatory enough?

Yes I can remove this comment,

Clément
>
> regards
> Philipp
>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock
  2019-11-05 13:57   ` Uwe Kleine-König
@ 2019-11-05 14:06     ` Clément Péron
  0 siblings, 0 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-05 14:06 UTC (permalink / raw)
  To: Uwe Kleine-König
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

Hi Uwe,

On Tue, 5 Nov 2019 at 14:57, Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> On Tue, Nov 05, 2019 at 02:14:52PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > H6 PWM core needs bus clock to be enabled in order to work.
> >
> > Add an optional probe for it and a fallback for previous
> > bindings without name on module clock.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 43 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index 9ba83769a478..54e19fa56a4e 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -78,6 +78,7 @@ struct sun4i_pwm_data {
> >
> >  struct sun4i_pwm_chip {
> >       struct pwm_chip chip;
> > +     struct clk *bus_clk;
> >       struct clk *clk;
> >       struct reset_control *rst;
> >       void __iomem *base;
> > @@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
> >       if (IS_ERR(pwm->base))
> >               return PTR_ERR(pwm->base);
> >
> > -     pwm->clk = devm_clk_get(&pdev->dev, NULL);
> > -     if (IS_ERR(pwm->clk))
> > +     /* Get all clocks and reset line */
> > +     pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
> > +     if (IS_ERR(pwm->clk)) {
> > +             dev_err(&pdev->dev, "get clock failed %ld\n",
> > +                     PTR_ERR(pwm->clk));
>
> Please only print this message if PTR_ERR(pwm->clk) != -EPROBE_DEFER.

I didn't do it because the sunxi clock can't be compiled as module but
indeed i can change it so it's more generic.

> You might also want to make use of commit 57f5677e535b ("printf: add
> support for printing symbolic error names") and use
>
>         dev_err(&pdev->dev, "get clock failed: %pe\n", pwm->clk);

Thanks I will change it,

Regards,
Clément

>
> Other than that the patch is fine for me.
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly
  2019-11-05 13:14 ` [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly Clément Péron
@ 2019-11-05 14:56   ` Uwe Kleine-König
  2019-11-06 21:24     ` Clément Péron
  0 siblings, 1 reply; 19+ messages in thread
From: Uwe Kleine-König @ 2019-11-05 14:56 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> PWM core has an option to bypass whole logic and output unchanged source
> clock as PWM output. This is achieved by enabling bypass bit.
> 
> Note that when bypass is enabled, no other setting has any meaning, not
> even enable bit.
> 
> This mode of operation is needed to achieve high enough frequency to
> serve as clock source for AC200 chip which is integrated into same
> package as H6 SoC.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index 54e19fa56a4e..810abf47c261 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -3,6 +3,10 @@
>   * Driver for Allwinner sun4i Pulse Width Modulation Controller
>   *
>   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
> + *
> + * Limitations:
> + * - When outputing the source clock directly, the PWM logic will be bypassed
> + *   and the currently running period is not guaranteed to be completed
>   */
>  
>  #include <linux/bitops.h>
> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
>  
>  struct sun4i_pwm_data {
>  	bool has_prescaler_bypass;
> +	bool has_direct_mod_clk_output;
>  	unsigned int npwm;
>  };
>  
> @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>  
>  	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>  
> +	/*
> +	 * PWM chapter in H6 manual has a diagram which explains that if bypass
> +	 * bit is set, no other setting has any meaning. Even more, experiment
> +	 * proved that also enable bit is ignored in this case.
> +	 */
> +	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> +	    sun4i_pwm->data->has_direct_mod_clk_output) {
> +		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> +		state->duty_cycle = state->period / 2;

Please round up here.

> +		state->polarity = PWM_POLARITY_NORMAL;
> +		state->enabled = true;
> +		return;
> +	}
> +
>  	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
>  	    sun4i_pwm->data->has_prescaler_bypass)
>  		prescaler = 1;
> @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  {
>  	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
>  	struct pwm_state cstate;
> -	u32 ctrl;
> +	u32 ctrl, clk_rate;
> +	bool bypass;
>  	int ret;
>  	unsigned int delay_us;
>  	unsigned long now;
> @@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  		}
>  	}
>  
> +	/*
> +	 * Although it would make much more sense to check for bypass in
> +	 * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
> +	 */
> +	clk_rate = clk_get_rate(sun4i_pwm->clk);

clk_get_rate must not be called if the clk might be off.

> +	bypass = state->enabled &&
> +		 (state->period * clk_rate >= NSEC_PER_SEC) &&

This is too coarse. With state->period = 1000000 this is fulfilled
(unless the multiplication overflows).

> +		 (state->duty_cycle * 2 == state->period);

This is too strict. See my previous mail about how this should be done.

If bypass is true (and the hardware support it) you can skip the
calculation of the other parameters.

> +
>  	spin_lock(&sun4i_pwm->ctrl_lock);
>  	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>  
> @@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>  		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
>  	}
>  
> +	if (sun4i_pwm->data->has_direct_mod_clk_output) {
> +		if (bypass)
> +			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> +		else
> +			ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
> +	}
> +
>  	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
>  
>  	spin_unlock(&sun4i_pwm->ctrl_lock);

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM
  2019-11-05 13:14 ` [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM Clément Péron
@ 2019-11-05 14:57   ` Uwe Kleine-König
  0 siblings, 0 replies; 19+ messages in thread
From: Uwe Kleine-König @ 2019-11-05 14:57 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

On Tue, Nov 05, 2019 at 02:14:54PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> Now that sun4i PWM driver supports deasserting reset line and enabling
> bus clock, support for H6 PWM can be added.
> 
> Note that while H6 PWM has two channels, only first one is wired to
> output pin. Second channel is used as a clock source to companion AC200
> chip which is bundled into same package.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Thanks
Uwe


-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description
  2019-11-05 13:14 ` [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron
@ 2019-11-05 21:33   ` Rob Herring
  0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2019-11-05 21:33 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, 'Uwe Kleine-König',
	Mark Rutland, Maxime Ripard, Chen-Yu Tsai, Philipp Zabel,
	linux-pwm, devicetree, linux-arm-kernel, linux-kernel,
	Jernej Skrabec

On Tue, Nov 05, 2019 at 02:14:50PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> H6 PWM block is basically the same as A20 PWM, except that it also has
> bus clock and reset line which needs to be handled accordingly.
> 
> Expand Allwinner PWM binding with H6 PWM specifics.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> index 0ac52f83a58c..9fc32c1d94b4 100644
> --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> @@ -30,13 +30,50 @@ properties:
>        - items:
>            - const: allwinner,sun50i-h5-pwm
>            - const: allwinner,sun5i-a13-pwm
> +      - const: allwinner,sun50i-h6-pwm
>  
>    reg:
>      maxItems: 1
>  
>    clocks:
> +    minItems: 1
> +    maxItems: 2
> +    items:
> +      - description: Bus Clock
> +      - description: Module Clock

The order here doesn't match the if/then or the example.

> +
> +  # Even though it only applies to subschemas under the conditionals,
> +  # not listing them here will trigger a warning because of the
> +  # additionalsProperties set to false.
> +  clock-names: true

blank line here.

> +  resets:
>      maxItems: 1
>  
> +  if:
> +    properties:
> +      compatible:
> +        contains:
> +          const: allwinner,sun50i-h6-pwm
> +
> +  then:
> +    properties:
> +      clocks:
> +        minItems: 2
> +
> +      clock-names:
> +        items:
> +          - const: mod
> +          - const: bus
> +
> +    required:
> +      - clock-names
> +      - resets
> +
> +  else:
> +    properties:
> +      clocks:
> +        maxItems: 1
> +
>  required:
>    - "#pwm-cells"
>    - compatible
> @@ -54,4 +91,14 @@ examples:
>          #pwm-cells = <3>;
>      };
>  
> +  - |
> +    pwm@300a000 {
> +      compatible = "allwinner,sun50i-h6-pwm";
> +      reg = <0x0300a000 0x400>;
> +      clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
> +      clock-names = "mod", "bus";
> +      resets = <&ccu RST_BUS_PWM>;
> +      #pwm-cells = <3>;
> +    };
> +
>  ...
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly
  2019-11-05 14:56   ` Uwe Kleine-König
@ 2019-11-06 21:24     ` Clément Péron
  2019-11-07  6:51       ` Uwe Kleine-König
  0 siblings, 1 reply; 19+ messages in thread
From: Clément Péron @ 2019-11-06 21:24 UTC (permalink / raw)
  To: Uwe Kleine-König
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

Hi Uwe,

On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote:
> > From: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > PWM core has an option to bypass whole logic and output unchanged source
> > clock as PWM output. This is achieved by enabling bypass bit.
> >
> > Note that when bypass is enabled, no other setting has any meaning, not
> > even enable bit.
> >
> > This mode of operation is needed to achieve high enough frequency to
> > serve as clock source for AC200 chip which is integrated into same
> > package as H6 SoC.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 37 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> > index 54e19fa56a4e..810abf47c261 100644
> > --- a/drivers/pwm/pwm-sun4i.c
> > +++ b/drivers/pwm/pwm-sun4i.c
> > @@ -3,6 +3,10 @@
> >   * Driver for Allwinner sun4i Pulse Width Modulation Controller
> >   *
> >   * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > + *
> > + * Limitations:
> > + * - When outputing the source clock directly, the PWM logic will be bypassed
> > + *   and the currently running period is not guaranteed to be completed
> >   */
> >
> >  #include <linux/bitops.h>
> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
> >
> >  struct sun4i_pwm_data {
> >       bool has_prescaler_bypass;
> > +     bool has_direct_mod_clk_output;
> >       unsigned int npwm;
> >  };
> >
> > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
> >
> >       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > +     /*
> > +      * PWM chapter in H6 manual has a diagram which explains that if bypass
> > +      * bit is set, no other setting has any meaning. Even more, experiment
> > +      * proved that also enable bit is ignored in this case.
> > +      */
> > +     if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> > +         sun4i_pwm->data->has_direct_mod_clk_output) {
> > +             state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> > +             state->duty_cycle = state->period / 2;
>
> Please round up here.
Ok
>
> > +             state->polarity = PWM_POLARITY_NORMAL;
> > +             state->enabled = true;
> > +             return;
> > +     }
> > +
> >       if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> >           sun4i_pwm->data->has_prescaler_bypass)
> >               prescaler = 1;
> > @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >  {
> >       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> >       struct pwm_state cstate;
> > -     u32 ctrl;
> > +     u32 ctrl, clk_rate;
> > +     bool bypass;
> >       int ret;
> >       unsigned int delay_us;
> >       unsigned long now;
> > @@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >               }
> >       }
> >
> > +     /*
> > +      * Although it would make much more sense to check for bypass in
> > +      * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
> > +      */
> > +     clk_rate = clk_get_rate(sun4i_pwm->clk);
>
> clk_get_rate must not be called if the clk might be off.
Ok,

>
> > +     bypass = state->enabled &&
> > +              (state->period * clk_rate >= NSEC_PER_SEC) &&
>
> This is too coarse. With state->period = 1000000 this is fulfilled
> (unless the multiplication overflows).

Sorry, misunderstood the previous mail

What about something like this ?
((state->period - 1) * clk_rate <= NSEC_PER_SEC) &&
((state->period + 1) * clk_rate >= NSEC_PER_SEC) &&
 ((state->duty_cycle - 1) * 2 <= state->period) &&
 ((state->duty_cycle + 1) * 2 >= state->period);

We are sure that the user is looking for a PWM around the OSC with a
50% duty cycle ?

Regards,
Clement

>
> > +              (state->duty_cycle * 2 == state->period);
>
> This is too strict. See my previous mail about how this should be done.
>
> If bypass is true (and the hardware support it) you can skip the
> calculation of the other parameters.
Yes correct and also we can skip


>
> > +
> >       spin_lock(&sun4i_pwm->ctrl_lock);
> >       ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > @@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> >               ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
> >       }
> >
> > +     if (sun4i_pwm->data->has_direct_mod_clk_output) {
> > +             if (bypass)
> > +                     ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> > +             else
> > +                     ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
> > +     }
> > +
> >       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
> >
> >       spin_unlock(&sun4i_pwm->ctrl_lock);
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly
  2019-11-06 21:24     ` Clément Péron
@ 2019-11-07  6:51       ` Uwe Kleine-König
  2019-11-08  8:34         ` Clément Péron
  0 siblings, 1 reply; 19+ messages in thread
From: Uwe Kleine-König @ 2019-11-07  6:51 UTC (permalink / raw)
  To: Clément Péron
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

Hello Clément,

On Wed, Nov 06, 2019 at 10:24:39PM +0100, Clément Péron wrote:
> On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König
> <u.kleine-koenig@pengutronix.de> wrote:
> > On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote:
> > > +     bypass = state->enabled &&
> > > +              (state->period * clk_rate >= NSEC_PER_SEC) &&
> >
> > This is too coarse. With state->period = 1000000 this is fulfilled
> > (unless the multiplication overflows).
> 
> Sorry, misunderstood the previous mail
> 
> What about something like this ?
> ((state->period - 1) * clk_rate <= NSEC_PER_SEC) &&
> ((state->period + 1) * clk_rate >= NSEC_PER_SEC) &&
>  ((state->duty_cycle - 1) * 2 <= state->period) &&
>  ((state->duty_cycle + 1) * 2 >= state->period);
> 
> We are sure that the user is looking for a PWM around the OSC with a
> 50% duty cycle ?

This again is too strict. The general policy to fulfill a request is:

 1) provide the longest possible period not bigger than requested
 2) provide the longest possible duty cycle not bigger than requested
 3) if possible complete the currently running period before switching
    and don't return to the user before the new setting is active.
    Document the behaviour prominently because the code (usually)
    doesn't allow to understand the hardware's features here.
 4) A disabled PWM should output the inactive level

And then there is a corner case: If the user requests .duty_cycle = 0,
.enabled = 1 it is ok to provide .enabled = 0 iff otherwise 0% isn't
possible.

So the right check for bypass is:

  state->period * clk_rate >= NSEC_PER_SEC &&
  state->period * clk_rate < whatevercanbereachedwithoutbypass &&
  state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly
  2019-11-07  6:51       ` Uwe Kleine-König
@ 2019-11-08  8:34         ` Clément Péron
  0 siblings, 0 replies; 19+ messages in thread
From: Clément Péron @ 2019-11-08  8:34 UTC (permalink / raw)
  To: Uwe Kleine-König
  Cc: Thierry Reding, Rob Herring, Mark Rutland, Maxime Ripard,
	Chen-Yu Tsai, Philipp Zabel, linux-pwm, devicetree,
	linux-arm-kernel, linux-kernel, Jernej Skrabec

Hi Uwe,

On Thu, 7 Nov 2019 at 07:51, Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> Hello Clément,
>
> On Wed, Nov 06, 2019 at 10:24:39PM +0100, Clément Péron wrote:
> > On Tue, 5 Nov 2019 at 15:57, Uwe Kleine-König
> > <u.kleine-koenig@pengutronix.de> wrote:
> > > On Tue, Nov 05, 2019 at 02:14:53PM +0100, Clément Péron wrote:
> > > > +     bypass = state->enabled &&
> > > > +              (state->period * clk_rate >= NSEC_PER_SEC) &&
> > >
> > > This is too coarse. With state->period = 1000000 this is fulfilled
> > > (unless the multiplication overflows).
> >
> > Sorry, misunderstood the previous mail
> >
> > What about something like this ?
> > ((state->period - 1) * clk_rate <= NSEC_PER_SEC) &&
> > ((state->period + 1) * clk_rate >= NSEC_PER_SEC) &&
> >  ((state->duty_cycle - 1) * 2 <= state->period) &&
> >  ((state->duty_cycle + 1) * 2 >= state->period);
> >
> > We are sure that the user is looking for a PWM around the OSC with a
> > 50% duty cycle ?
>
> This again is too strict. The general policy to fulfill a request is:
>
>  1) provide the longest possible period not bigger than requested
>  2) provide the longest possible duty cycle not bigger than requested
>  3) if possible complete the currently running period before switching
>     and don't return to the user before the new setting is active.
>     Document the behaviour prominently because the code (usually)
>     doesn't allow to understand the hardware's features here.
>  4) A disabled PWM should output the inactive level

Thanks for the explanation

>
> And then there is a corner case: If the user requests .duty_cycle = 0,
> .enabled = 1 it is ok to provide .enabled = 0 iff otherwise 0% isn't
> possible.
>
> So the right check for bypass is:
>
>   state->period * clk_rate >= NSEC_PER_SEC &&
>   state->period * clk_rate < whatevercanbereachedwithoutbypass &&
>   state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC

The shortest PWM ratio which is not a constant output is 12MHz.
(Prescal 1, 2 entire cycle and 1 active cycle)

So something like this :
state->period * clk_rate >= NSEC_PER_SEC &&
state->period * clk_rate < 2 * NSEC_PER_SEC &&
state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC

I will send a v4,
Thanks for the help
Regards,
Clément

>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2019-11-08  8:34 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-05 13:14 [PATCH v3 0/7] Add support for H6 PWM Clément Péron
2019-11-05 13:14 ` [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Clément Péron
2019-11-05 21:33   ` Rob Herring
2019-11-05 13:14 ` [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Clément Péron
2019-11-05 13:36   ` Philipp Zabel
2019-11-05 14:01     ` Clément Péron
2019-11-05 13:53   ` Uwe Kleine-König
2019-11-05 13:14 ` [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock Clément Péron
2019-11-05 13:57   ` Uwe Kleine-König
2019-11-05 14:06     ` Clément Péron
2019-11-05 13:14 ` [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly Clément Péron
2019-11-05 14:56   ` Uwe Kleine-König
2019-11-06 21:24     ` Clément Péron
2019-11-07  6:51       ` Uwe Kleine-König
2019-11-08  8:34         ` Clément Péron
2019-11-05 13:14 ` [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM Clément Péron
2019-11-05 14:57   ` Uwe Kleine-König
2019-11-05 13:14 ` [PATCH v3 6/7] arm64: dts: allwinner: h6: Add PWM node Clément Péron
2019-11-05 13:14 ` [PATCH v3 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Clément Péron

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