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Thu, 7 Nov 2019 08:41:48 +0000 From: To: , CC: , , , , Subject: [PATCH v5 0/6] mtd: spi-nor: Quad Enable and (un)lock methods Thread-Topic: [PATCH v5 0/6] mtd: spi-nor: Quad Enable and (un)lock methods Thread-Index: AQHVlUcxNfurCR7UA0az+I+u2JP03g== Date: Thu, 7 Nov 2019 08:41:47 +0000 Message-ID: <20191107084135.22122-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR10CA0060.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::40) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [109.166.128.4] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 922a89c4-25b6-47d0-fbfd-08d7635e536f x-ms-traffictypediagnostic: MN2PR11MB3824: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 0214EB3F68 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(136003)(396003)(366004)(376002)(39860400002)(346002)(189003)(199004)(25786009)(6512007)(66476007)(6486002)(110136005)(66946007)(6116002)(66446008)(71200400001)(86362001)(54906003)(66556008)(64756008)(2906002)(6436002)(14444005)(256004)(36756003)(478600001)(66066001)(14454004)(8936002)(186003)(52116002)(316002)(2616005)(99286004)(102836004)(71190400001)(107886003)(81156014)(81166006)(4326008)(2501003)(26005)(1076003)(305945005)(7736002)(6506007)(5660300002)(486006)(476003)(386003)(8676002)(3846002)(50226002)(473944003)(414714003);DIR:OUT;SFP:1101;SCL:1;SRVR:MN2PR11MB3824;H:MN2PR11MB4448.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: pXm32/gEVZJrQZR4tUnVwRMTuW0g5a/tYULXO/TKjxsR+3dJfUsynedzo86g+4sGcaxxQDTLW5grPzp70itv8MXb3ooxHMzufrhWVGjdA2VknDG53Om1hKK3HuFTaDbGEkSuqetzZXzdbBEfASTsJ8em14QsUJuDuxlYoK+u1Ouvu+IGVxmaKthGN7aRp5pmtdwDBvo24HF5EaaGKtCGY5nx8Eb55CoQcgt6VVYysFUmEZsoJVwzuJYM+5H8+2so2T4aobAI45N9SUp8BuQUl4U+tOIe8Dfcoe6Tr9QHHtuxPKZB4NRm24VvYgIFbdq+IPm7+UCPc0FhHilzMnRREHUS44vawszxAAVQF++YgGNzcHx9KyI6rW4kYpDLuSkJdPRLwdK3UGZvxMsUOB14JhEUO8ac/T3oTvzPCbp4fEHkEiG2M63tTA4WOxKmdVmN Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 922a89c4-25b6-47d0-fbfd-08d7635e536f X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2019 08:41:47.9524 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XKSsrGZ96Bvn/kId5eSOltrXrEXOKBWG7nhB/1Af6OHG3NLITl1dVP90eobRD3Dikl9WTcot8BhBpGD2aAq+6ulKjTbr8Dcxr6MuTDwN+Kk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3824 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Tested on w25q128jvq. Fixed the clearing of QE bit on (un)lock() operations. Reworked the Quad Enable methods and the disabling of the block write protection at power-up. v5: - Rename all Quad Enable methods in one patch - Extend the Read Back test to both SR1 and SR2 in one patch - Reorder patches, so that the fixes come one after another - Collect R-b tags. v4: - Use dev_dbg insted of dev_err for low level info - replace "&nor->bouncebuf[0]" with "nor->bouncebuf" and "&sr_cr[0]" with "sr_cr". Update across all patches. v3: split patches, update retlen handling in sst_write. v2: - Introduce spi_nor_write_16bit_cr_and_check() as per Vignesh's suggestion.= The Configuration Register contains bits that can be updated in future: FREEZ= E, CMP. Provide a generic method that allows updating all bits of the Configuration Register. - Fix SNOR_F_NO_READ_CR case in "mtd: spi-nor: Rework the disabling of block write protection". When the = flash doesn't support the CR Read command, we make an assumption about the valu= e of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be = sure the QE bit has value one, because of the previous call to spi_nor_quad_en= able(). - Fix if statement in spi_nor_write_sr_and_check(): if (nor->flags & SNOR_F_HAS_16BIT_SR) - Fix documentation warnings. - New patch: "mtd: spi-nor: Check all the bits written, not just the BP one= s". - Drop Global Unlock patches, will send them in a different patch set. The patch set can be tested using mtd-utils: 1/ do a read-erase-write-read-back test immediately after boot, to check the spi_nor_unlock_all() method. The focus is on the erase/write methods, we want to see if the flash is unlocked at power-up. mtd_debug read /dev/mtd-yours offset size read-file hexdump read-file mtd_debug erase /dev/mtd-yours offset size dd if=3D/dev/urandom of=3Dwrite-file bs=3Dplease-choose count=3Dple= ase-choose mtd_debug write /dev/mtd-yours offset write-file-size write-file mtd_debug read /dev/mtd-yours offset write-file-size read-file sha1sum read-file write-file 2/ lock flash then try to erase/write it, to see if the lock works flash_lock /dev/mtd-yours offset block-count Do the read-erase-write-read-back test from 1/. The contents of flash should not change in the erase and write steps. 3/ unlock flash and do the read-erase-write-read-back from 1/. The value of= the QEE should not change and you should be able to erase and write the flas= h. Test 1/ should be successful. Tudor Ambarus (6): mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() mtd: spi-nor: Rework the disabling of block write protection mtd: spi-nor: Extend the SR Read Back test mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 mtd: spi-nor: Merge spansion Quad Enable methods mtd: spi-nor: Rename Quad Enable methods drivers/mtd/spi-nor/spi-nor.c | 438 ++++++++++++++++++++++++--------------= ---- include/linux/mtd/spi-nor.h | 12 +- 2 files changed, 254 insertions(+), 196 deletions(-) --=20 2.9.5