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Thu, 7 Nov 2019 08:41:51 +0000 From: To: , CC: , , , , Subject: [PATCH v5 1/6] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Topic: [PATCH v5 1/6] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Thread-Index: AQHVlUczkwfs0dXIv02WLfMaDwkFYQ== Date: Thu, 7 Nov 2019 08:41:51 +0000 Message-ID: <20191107084135.22122-2-tudor.ambarus@microchip.com> References: <20191107084135.22122-1-tudor.ambarus@microchip.com> In-Reply-To: <20191107084135.22122-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR10CA0060.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::40) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [109.166.128.4] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cb5fd03c-4d0a-49d7-30b8-08d7635e5540 x-ms-traffictypediagnostic: MN2PR11MB3824: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: cb5fd03c-4d0a-49d7-30b8-08d7635e5540 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2019 08:41:51.7412 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: P6vm9KMFgh5r/WCwjJanMtHg6R9PmvBxJcrOUn5liKZIoI75Q2cyA8TWDAuwVCtt+eFDKnsU1GecUd30wS+TvqGdFY0+YmU0XKMID4nxEUc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3824 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 120 ++++++++++++++++++++++++++++++++++++++= ++-- include/linux/mtd/spi-nor.h | 3 ++ 2 files changed, 118 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 9960e09136ce..d696334f25f0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -959,12 +959,19 @@ static int spi_nor_write_sr(struct spi_nor *nor, cons= t u8 *sr, size_t len) return spi_nor_wait_till_ready(nor); } =20 -/* Write status register and ensure bits in mask match written values */ -static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new) +/** + * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1= and + * ensure that the byte written match the received value. + * @nor: pointer to a 'struct spi_nor'. + * @sr1: byte value to be written to the Status Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) { int ret; =20 - nor->bouncebuf[0] =3D status_new; + nor->bouncebuf[0] =3D sr1; =20 ret =3D spi_nor_write_sr(nor, nor->bouncebuf, 1); if (ret) @@ -974,8 +981,73 @@ static int spi_nor_write_sr_and_check(struct spi_nor *= nor, u8 status_new) if (ret) return ret; =20 - if (nor->bouncebuf[0] !=3D status_new) { - dev_dbg(nor->dev, "SR: read back test failed\n"); + if (nor->bouncebuf[0] !=3D sr1) { + dev_dbg(nor->dev, "SR1: read back test failed\n"); + return -EIO; + } + + return 0; +} + +/** + * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and th= e + * Status Register 2 in one shot. Ensure that the byte written in the Stat= us + * Register 1 match the received value, and that the 16-bit Write did not + * affect what was already in the Status Register 2. + * @nor: pointer to a 'struct spi_nor'. + * @sr1: byte value to be written to the Status Register 1. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) +{ + int ret; + u8 *sr_cr =3D nor->bouncebuf; + u8 cr_written; + + /* Make sure we don't overwrite the contents of Status Register 2. */ + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) + return ret; + } else if (nor->params.quad_enable) { + /* + * If the Status Register 2 Read command (35h) is not + * supported, we should at least be sure we don't + * change the value of the SR2 Quad Enable bit. + * + * We can safely assume that when the Quad Enable method is + * set, the value of the QE bit is one, as a consequence of the + * nor->params.quad_enable() call. + * + * We can safely assume that the Quad Enable bit is present in + * the Status Register 2 at BIT(1). According to the JESD216 + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit + * Write Status (01h) command is available just for the cases + * in which the QE bit is described in SR2 at BIT(1). + */ + sr_cr[1] =3D CR_QUAD_EN_SPAN; + } else { + sr_cr[1] =3D 0; + } + + sr_cr[0] =3D sr1; + + ret =3D spi_nor_write_sr(nor, sr_cr, 2); + if (ret) + return ret; + + if (nor->flags & SNOR_F_NO_READ_CR) + return 0; + + cr_written =3D sr_cr[1]; + + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) + return ret; + + if (cr_written !=3D sr_cr[1]) { + dev_dbg(nor->dev, "CR: read back test failed\n"); return -EIO; } =20 @@ -983,6 +1055,23 @@ static int spi_nor_write_sr_and_check(struct spi_nor = *nor, u8 status_new) } =20 /** + * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure t= hat + * the byte written match the received value without affecting other bits = in the + * Status Register 1 and 2. + * @nor: pointer to a 'struct spi_nor'. + * @sr1: byte value to be written to the Status Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) +{ + if (nor->flags & SNOR_F_HAS_16BIT_SR) + return spi_nor_write_16bit_sr_and_check(nor, sr1); + + return spi_nor_write_sr1_and_check(nor, sr1); +} + +/** * spi_nor_write_sr2() - Write the Status Register 2 using the * SPINOR_OP_WRSR2 (3eh) command. * @nor: pointer to 'struct spi_nor'. @@ -3634,19 +3723,38 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; =20 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: + /* + * Writing only one byte to the Status Register has the + * side-effect of clearing Status Register 2. + */ case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: + /* + * Read Configuration Register (35h) instruction is not + * supported. + */ + nor->flags |=3D SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; params->quad_enable =3D spansion_no_read_cr_quad_enable; break; =20 case BFPT_DWORD15_QER_SR1_BIT6: + nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; params->quad_enable =3D macronix_quad_enable; break; =20 case BFPT_DWORD15_QER_SR2_BIT7: + nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; params->quad_enable =3D sr2_bit7_quad_enable; break; =20 case BFPT_DWORD15_QER_SR2_BIT1: + /* + * JESD216 rev B or later does not specify if writing only one + * byte to the Status Register clears or not the Status + * Register 2, so let's be cautious and keep the default + * assumption of a 16-bit Write Status (01h) command. + */ + nor->flags |=3D SNOR_F_HAS_16BIT_SR; + params->quad_enable =3D spansion_read_cr_quad_enable; break; =20 @@ -4613,6 +4721,8 @@ static void spi_nor_info_init_params(struct spi_nor *= nor) params->quad_enable =3D spansion_read_cr_quad_enable; params->set_4byte =3D spansion_set_4byte; params->setup =3D spi_nor_default_setup; + /* Default to 16-bit Write Status (01h) Command */ + nor->flags |=3D SNOR_F_HAS_16BIT_SR; =20 /* Set SPI NOR sizes. */ params->size =3D (u64)info->sector_size * info->n_sectors; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1d736d3c8ab..d6ec55cc6d97 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -243,6 +243,9 @@ enum spi_nor_option_flags { SNOR_F_4B_OPCODES =3D BIT(6), SNOR_F_HAS_4BAIT =3D BIT(7), SNOR_F_HAS_LOCK =3D BIT(8), + SNOR_F_HAS_16BIT_SR =3D BIT(9), + SNOR_F_NO_READ_CR =3D BIT(10), + }; =20 /** --=20 2.9.5