From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 566BEC5DF61 for ; Thu, 7 Nov 2019 10:37:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AAAF2085B for ; Thu, 7 Nov 2019 10:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388141AbfKGKhK (ORCPT ); Thu, 7 Nov 2019 05:37:10 -0500 Received: from foss.arm.com ([217.140.110.172]:53890 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfKGKhJ (ORCPT ); Thu, 7 Nov 2019 05:37:09 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB1091FB; Thu, 7 Nov 2019 02:37:08 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 50D633F71A; Thu, 7 Nov 2019 02:37:08 -0800 (PST) Date: Thu, 7 Nov 2019 10:37:06 +0000 From: Andrew Murray To: Nicolas Saenz Julienne Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland , Eric Anholt , Stefan Wahren , james.quinlan@broadcom.com, mbrugger@suse.com, f.fainelli@gmail.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Message-ID: <20191107103705.GX9723@e119886-lin.cambridge.arm.com> References: <20191106214527.18736-1-nsaenzjulienne@suse.de> <20191106214527.18736-3-nsaenzjulienne@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191106214527.18736-3-nsaenzjulienne@suse.de> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 06, 2019 at 10:45:24PM +0100, Nicolas Saenz Julienne wrote: > This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies s/wich/which/ > XHCI USB 3.0 controller. > > Signed-off-by: Nicolas Saenz Julienne > --- > arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi > index a9d84e28f245..c7b2e7b57da6 100644 > --- a/arch/arm/boot/dts/bcm2711.dtsi > +++ b/arch/arm/boot/dts/bcm2711.dtsi > @@ -288,6 +288,53 @@ > arm,cpu-registers-not-fw-configured; > }; > > + scb { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, > + <0x6 0x00000000 0x6 0x00000000 0x40000000>; > + > + pcie_0: pcie@7d500000 { > + compatible = "brcm,bcm2711-pcie"; > + reg = <0x0 0x7d500000 0x9310>; > + msi-controller; > + msi-parent = <&pcie_0>; > + #address-cells = <3>; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + linux,pci-domain = <0>; pci-domain is unlikely to be needed here. > + brcm,enable-ssc; > + interrupts = , > + ; > + interrupt-names = "pcie", "msi"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 > + IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gicv2 GIC_SPI 144 > + IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gicv2 GIC_SPI 145 > + IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gicv2 GIC_SPI 146 > + IRQ_TYPE_LEVEL_HIGH>; > + > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 > + 0x0 0x04000000>; Is legacy I/O supported by this controller? > + /* > + * The wrapper around the PCIe block has a bug > + * preventing it from accessing beyond the first 3GB of > + * memory. As the bus DMA mask is rounded up to the > + * closest power of two of the dma-range size, we're > + * forced to set the limit at 2GB. This can be > + * harmlessly changed in the future once the DMA code > + * handles non power of two DMA limits. > + */ > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 > + 0x0 0x80000000>; > + }; > + }; Thanks, Andrew Murray > + > cpus: cpus { > #address-cells = <1>; > #size-cells = <0>; > -- > 2.23.0 >