From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89E18FA372C for ; Fri, 8 Nov 2019 17:01:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54483222C5 for ; Fri, 8 Nov 2019 17:01:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573232517; bh=67JDj4r+jAAkc4Ug4xJADR1bD+ChmxDXFWZf+bpy2BY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=gDGwCN2wwcpnM2AHWKqpvjbUrKLj2E9K350tqkqTj7RrzGadZx79Hu1BfWEapaYK0 T6kDNmzsk3gS9kSYYfVDxaJaF8XHjXO6k7mujyWGyqdrz4pJnDGBWLVUgc51A7hH5w QyjjlQ48vEfQRl/ipHst4yqMnlrwpRtwnrQJ4VWw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730958AbfKHRB4 (ORCPT ); Fri, 8 Nov 2019 12:01:56 -0500 Received: from mail.kernel.org ([198.145.29.99]:45858 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730813AbfKHRBy (ORCPT ); Fri, 8 Nov 2019 12:01:54 -0500 Received: from localhost.localdomain (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5F1F621924; Fri, 8 Nov 2019 17:01:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573232513; bh=67JDj4r+jAAkc4Ug4xJADR1bD+ChmxDXFWZf+bpy2BY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TJseonJhz9WQuIXAL2GmXjJ61Otkf3PnP8mI4NcBFT47u1GaXNq1ChqCsHcPOfJ1N +xdVgVpjfiTHtRPewxr1qXM4+fbnRSSw76pC5pg1Ul/MF0tT3+Hk9xwIR49TV3fN/1 CeZFTg5qigtDvPpIbDcsPTxcxe9R5drSoFMDLRys= From: Will Deacon To: linux-kernel@vger.kernel.org Cc: Will Deacon , Yunjae Lee , SeongJae Park , "Paul E. McKenney" , Josh Triplett , Matt Turner , Ivan Kokshaysky , Richard Henderson , Peter Zijlstra , Alan Stern , Michael Ellerman , "Michael S. Tsirkin" , Jason Wang , Arnd Bergmann , Joe Perches , Boqun Feng , linux-alpha@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: [PATCH 07/13] alpha: Replace smp_read_barrier_depends() usage with smp_[r]mb() Date: Fri, 8 Nov 2019 17:01:14 +0000 Message-Id: <20191108170120.22331-8-will@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108170120.22331-1-will@kernel.org> References: <20191108170120.22331-1-will@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for removing 'smp_read_barrier_depends()' altogether, move the Alpha code over to using 'smp_rmb()' and 'smp_mb()' directly. Signed-off-by: Will Deacon --- arch/alpha/include/asm/atomic.h | 16 ++++++++-------- arch/alpha/include/asm/pgtable.h | 10 +++++----- mm/memory.c | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h index 2144530d1428..2f8f7e54792f 100644 --- a/arch/alpha/include/asm/atomic.h +++ b/arch/alpha/include/asm/atomic.h @@ -16,10 +16,10 @@ /* * To ensure dependency ordering is preserved for the _relaxed and - * _release atomics, an smp_read_barrier_depends() is unconditionally - * inserted into the _relaxed variants, which are used to build the - * barriered versions. Avoid redundant back-to-back fences in the - * _acquire and _fence versions. + * _release atomics, an smp_mb() is unconditionally inserted into the + * _relaxed variants, which are used to build the barriered versions. + * Avoid redundant back-to-back fences in the _acquire and _fence + * versions. */ #define __atomic_acquire_fence() #define __atomic_post_full_fence() @@ -70,7 +70,7 @@ static inline int atomic_##op##_return_relaxed(int i, atomic_t *v) \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ - smp_read_barrier_depends(); \ + smp_mb(); \ return result; \ } @@ -88,7 +88,7 @@ static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v) \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ - smp_read_barrier_depends(); \ + smp_mb(); \ return result; \ } @@ -123,7 +123,7 @@ static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ - smp_read_barrier_depends(); \ + smp_mb(); \ return result; \ } @@ -141,7 +141,7 @@ static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \ ".previous" \ :"=&r" (temp), "=m" (v->counter), "=&r" (result) \ :"Ir" (i), "m" (v->counter) : "memory"); \ - smp_read_barrier_depends(); \ + smp_mb(); \ return result; \ } diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index 065b57f408c3..b807793646c7 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h @@ -288,9 +288,9 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; } #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) /* - * The smp_read_barrier_depends() in the following functions are required to - * order the load of *dir (the pointer in the top level page table) with any - * subsequent load of the returned pmd_t *ret (ret is data dependent on *dir). + * The smp_rmb() in the following functions are required to order the load of + * *dir (the pointer in the top level page table) with any subsequent load of + * the returned pmd_t *ret (ret is data dependent on *dir). * * If this ordering is not enforced, the CPU might load an older value of * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for @@ -304,7 +304,7 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; } extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) { pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); - smp_read_barrier_depends(); /* see above */ + smp_rmb(); /* see above */ return ret; } @@ -313,7 +313,7 @@ extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address) { pte_t *ret = (pte_t *) pmd_page_vaddr(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1)); - smp_read_barrier_depends(); /* see above */ + smp_rmb(); /* see above */ return ret; } diff --git a/mm/memory.c b/mm/memory.c index b1ca51a079f2..c4a74e6d2c5c 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -420,7 +420,7 @@ int __pte_alloc(struct mm_struct *mm, pmd_t *pmd) * of a chain of data-dependent loads, meaning most CPUs (alpha * being the notable exception) will already guarantee loads are * seen in-order. See the alpha page table accessors for the - * smp_read_barrier_depends() barriers in page table walking code. + * smp_rmb() barriers in page table walking code. */ smp_wmb(); /* Could be smp_wmb__xxx(before|after)_spin_lock */ -- 2.24.0.rc1.363.gb1bccd3e3d-goog