From: Andrew Lunn <andrew@lunn.ch>
To: Vladimir Oltean <olteanv@gmail.com>
Cc: shawnguo@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, leoyang.li@nxp.com,
robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs
Date: Sat, 9 Nov 2019 16:09:53 +0100 [thread overview]
Message-ID: <20191109150953.GJ22978@lunn.ch> (raw)
In-Reply-To: <20191109105642.30700-1-olteanv@gmail.com>
On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote:
> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1
> have interrupt lines connected to the shared IRQ2_B LS1021A pin.
>
> The interrupts are active low, but the GICv2 controller does not support
> active-low and falling-edge interrupts, so the only mode it can be
> configured in is rising-edge.
Hi Vladimir
So how does this work? The rising edge would occur after the interrupt
handler has completed? What triggers the interrupt handler?
Andrew
next prev parent reply other threads:[~2019-11-09 15:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-09 10:56 [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs Vladimir Oltean
2019-11-09 15:09 ` Andrew Lunn [this message]
2019-11-09 15:21 ` Vladimir Oltean
2019-11-09 19:52 ` Alexander Stein
2019-11-09 21:05 ` Andrew Lunn
2019-11-09 21:37 ` Vladimir Oltean
2019-11-09 21:56 ` Vladimir Oltean
[not found] ` <CA+h21hrqczuOhTzWFZKX0XvgjgTzHT=3AdCPvO_eSabOzA3OCQ@mail.gmail.com>
2019-11-09 17:21 ` Andrew Lunn
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