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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h23sm20982195pgg.58.2019.11.18.17.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 17:05:50 -0800 (PST) Date: Mon, 18 Nov 2019 17:05:47 -0800 From: Bjorn Andersson To: Lina Iyer Cc: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org Subject: Re: [PATCH v2 00/12] Support wakeup capable GPIOs Message-ID: <20191119010547.GN36595@minitux> References: <1573855915-9841-1-git-send-email-ilina@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1573855915-9841-1-git-send-email-ilina@codeaurora.org> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 15 Nov 14:11 PST 2019, Lina Iyer wrote: > Hi, > > Here is the spin of the series with the review comments addressed and > Reviewed-by tags added. Thanks all for your reviews. > > Andy/Bjorn, would you pull patches 10-12 in your tree? Marc would be > pulling the patches 1-9 into the irqchip tree. > Patches 10-12 picked up for v5.6 Regards, Bjorn > Thanks. > > --Lina > > --- > Changes in v2: > - Address review comments > - Added Reviewed-by tags > > Changes in v1[7]: > - Address review comments > - Add Reviewed-by tags > - Drop SPI config patches > - Rebase on top of Rajendra's PDC changes [6] > > Changes in RFC v2[5]: > - Address review comments #3, #4, #6, #7, #8, #9, #10 > - Rebased on top of linux-next GPIO latest patches [1],[3],[4] > - Increase PDC max irqs in #2 (avoid merge conflicts with > downstream) > - Add Reviewed-by #5 > > > [1]. > https://lore.kernel.org/linux-gpio/20190808123242.5359-1-linus.walleij@linaro.org/ > [2]. > https://lkml.org/lkml/2019/5/7/1173 > [3]. > https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.org > [4]. > https://lore.kernel.org/r/20190724083828.7496-1-linus.walleij@linaro.org > [5]. > https://lore.kernel.org/linux-gpio/5da6b849.1c69fb81.a9b04.1b9f@mx.google.com/t/ > [6]. > https://lore.kernel.org/linux-arm-msm/d622482d92059533f03b65af26c69b9b@www.loen.fr/ > [7]. > https://lore.kernel.org/linux-gpio/5dcefdfd.1c69fb81.c5332.fbe0@mx.google.com/T/#t > > Lina Iyer (10): > irqdomain: add bus token DOMAIN_BUS_WAKEUP > drivers: irqchip: qcom-pdc: update max PDC interrupts > drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask > drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs > of: irq: document properties for wakeup interrupt parent > drivers: pinctrl: msm: setup GPIO chip in hierarchy > drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs > arm64: dts: qcom: add PDC interrupt controller for SDM845 > arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 > arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 > > Maulik Shah (2): > genirq: Introduce irq_chip_get/set_parent_state calls > drivers: irqchip: pdc: Add irqchip set/get state calls > > .../bindings/interrupt-controller/interrupts.txt | 12 ++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++ > arch/arm64/configs/defconfig | 1 + > drivers/irqchip/qcom-pdc.c | 147 +++++++++++++++++++-- > drivers/pinctrl/qcom/pinctrl-msm.c | 112 +++++++++++++++- > drivers/pinctrl/qcom/pinctrl-msm.h | 14 ++ > drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 +++- > include/linux/irq.h | 6 + > include/linux/irqdomain.h | 1 + > include/linux/soc/qcom/irq.h | 34 +++++ > kernel/irq/chip.c | 44 ++++++ > 11 files changed, 388 insertions(+), 16 deletions(-) > create mode 100644 include/linux/soc/qcom/irq.h > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >