From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE7AC432C0 for ; Tue, 19 Nov 2019 05:53:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F41A20721 for ; Tue, 19 Nov 2019 05:53:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574142781; bh=oHMUJSdY6GTcK8AEGZQrARA28E+MfxcypOGkikh7IlM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=flEZzTguYO1fkQroqTFOtBP+Q7DXmI9lEf7RDk3NvkGNlAasQkV1QkgPAT1dlEjhS vmZaUhIcZW4T3/P4d3bJuSxEPVJ14VXb/oRROmx3+Nh5Aw9SgALVgCBEOL8U49obvg Te0HFEQ8InESfbTPrFxOLhWIlWDZWHaABohMscGY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731344AbfKSFxA (ORCPT ); Tue, 19 Nov 2019 00:53:00 -0500 Received: from mail.kernel.org ([198.145.29.99]:50754 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731961AbfKSFwy (ORCPT ); Tue, 19 Nov 2019 00:52:54 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5CE5221939; Tue, 19 Nov 2019 05:52:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574142773; bh=oHMUJSdY6GTcK8AEGZQrARA28E+MfxcypOGkikh7IlM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aniEgnHukkFHqBb+ibfpEDoZKRrDoARwNv54Pae69dDQVpTp01+v2JxGRKMnuV930 lnxBeslCkow1u5hzgLX6WeisUbddg60bt2Paau/QFQ600fL+aHFlYbc5cwQ/v1OEI5 H6/86w0vGDHQLcTe9AC0ryNe5++xjYih+W4wv8Qo= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Mathieu Poirier , Mike Leach , Leo Yan , Sasha Levin Subject: [PATCH 4.14 195/239] coresight: tmc: Fix byte-address alignment for RRP Date: Tue, 19 Nov 2019 06:19:55 +0100 Message-Id: <20191119051335.964672784@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191119051255.850204959@linuxfoundation.org> References: <20191119051255.850204959@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan [ Upstream commit e7753f3937610633a540f2be81be87531f96ff04 ] >>From the comment in the code, it claims the requirement for byte-address alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s'. This isn't consistent with the program, the program sets five LSBs as zeros for 32/64/128-bit wide trace memory and set six LSBs zeros for 256-bit wide trace memory. After checking with the CoreSight Trace Memory Controller technical reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer Register), it proves the comment is right and the program does wrong setting. This patch fixes byte-address alignment for RRP by following correct definition in the technical reference manual. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Leo Yan Signed-off-by: Mathieu Poirier Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index e2513b7862427..336194d059fed 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -442,10 +442,10 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, case TMC_MEM_INTF_WIDTH_32BITS: case TMC_MEM_INTF_WIDTH_64BITS: case TMC_MEM_INTF_WIDTH_128BITS: - mask = GENMASK(31, 5); + mask = GENMASK(31, 4); break; case TMC_MEM_INTF_WIDTH_256BITS: - mask = GENMASK(31, 6); + mask = GENMASK(31, 5); break; } -- 2.20.1