* [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check
@ 2019-11-20 6:10 Lu Baolu
2019-12-18 15:18 ` Joerg Roedel
0 siblings, 1 reply; 2+ messages in thread
From: Lu Baolu @ 2019-11-20 6:10 UTC (permalink / raw)
To: Joerg Roedel, David Woodhouse
Cc: ashok.raj, jacob.jun.pan, kevin.tian, iommu, linux-kernel,
Lu Baolu, Jacob Pan
The PSI (Page Selective Invalidation) bit in the capability register
is only valid for second-level translation. Intel IOMMU supporting
scalable mode must support page/address selective IOTLB invalidation
for first-level translation. Remove the PSI capability check in SVA
cache invalidation code.
Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel-svm.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 9b159132405d..dca88f9fdf29 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
{
struct qi_desc desc;
- /*
- * Do PASID granu IOTLB invalidation if page selective capability is
- * not available.
- */
- if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) {
+ if (pages == -1) {
desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
QI_EIOTLB_DID(sdev->did) |
QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check
2019-11-20 6:10 [PATCH 1/1] iommu/vt-d: Remove incorrect PSI capability check Lu Baolu
@ 2019-12-18 15:18 ` Joerg Roedel
0 siblings, 0 replies; 2+ messages in thread
From: Joerg Roedel @ 2019-12-18 15:18 UTC (permalink / raw)
To: Lu Baolu
Cc: David Woodhouse, ashok.raj, jacob.jun.pan, kevin.tian, iommu,
linux-kernel, Jacob Pan
On Wed, Nov 20, 2019 at 02:10:16PM +0800, Lu Baolu wrote:
> The PSI (Page Selective Invalidation) bit in the capability register
> is only valid for second-level translation. Intel IOMMU supporting
> scalable mode must support page/address selective IOTLB invalidation
> for first-level translation. Remove the PSI capability check in SVA
> cache invalidation code.
>
> Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel-svm.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
Applied for v5.5, thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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