[PATCH v5 0/9] ARM: Realtek RTD1195/RTD1295/RTD1395 IRQ mux

[PATCH v5 0/9] ARM: Realtek RTD1195/RTD1295/RTD1395 IRQ mux

[Andreas Färber]

Hello,

This series adds two IRQ muxes for the Realtek RTD1195, RTD1295 and RTD1395
SoC families.

The implementation is based on register offsets seen in the vendor DT,
split up into two separate nodes, as well as code from QNAP's rtk119x and
Synology's RTD1293/96 GPL code dumps and Banana Bi W2/M4 BSP repositories.

v5 cleans up mask/unmask, ack and naming.

From /proc/interrupts on RTD1195:
 24:        158       iso   2 Edge      ttyS0

From /proc/interrupts on RTD1395:
  9:        110          0          0          0       iso   2 Edge      ttyS0

The chip name now no longer overflows the columns, but irq type is still wrong.

@Realtek: Patch 8/9 contains a question about RTD1395.

More experimental patches at:
https://github.com/afaerber/linux/commits/rtd1295-next

Have a lot of fun!

Cheers,
Andreas

v4 -> v5:
* Renamed enable/disable to unmask/mask (Marc)
* Factored out ack (Marc)
* Clear all interrupts
* Mapped RTD1195 WDOG_NMI
* Added and mapped RTD1295 WDOG_NMI
* Suppress mapping NMIs and reserved bits (Marc)
* Drop mask checks in mask/unmask (Marc)
* Drop mask check in interrupt handler
* Renamed RTD1295 misc bits with MIS_ for consistency
* Renamed RTD1395 misc bits from MISC_ to MIS_ for consistency
* Renamed irq_chip to distinguish iso vs. misc
* Implemented .irq_get_irqchip_state

v3 -> v4:
* Drop no-op .irq_set_affinity callback (Thomas)
* Disable all interrupts (James)
* Updated SPDX-License-identifier
* Use tabular formatting (Thomas)
* Adopt different braces style (Thomas)
* Use raw_spinlock_t (Thomas)
* Shortened callback name (Thomas)
* Fixed of_iomap() error handling
* Don't mask unmapped NMIs
* Cache SCPU_INT_EN (Thomas)
* Renamed binding and source files
* Dropped UART1/UART2 TO interrupts
* Expanded commit messages
* Added RTD1395 patches

v2 -> v3:
* Rebased, adding nodes to rtd129x.dtsi instead of rtd1295.dtsi
* Adopted {readl,writel}_relaxed() (Marc)
* Adopted spin_lock_irqsave() (Marc)
* Implemented RTD1195
* Implemented mapping for non-linear bits such as i2c3

v1 -> v2:
* Rebased, avoiding dependency on reset series for DT nodes
* Don't forward set_affinity to GIC (Marc)
* Added more spinlocks (Marc)
* Code cleanups
* Investigated quirk
* Fixed spinlock initialization (Andrew)

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Aleix Roca Nonell <kernelrocks@gmail.com>
Cc: James Tai <james.tai@realtek.com>

Andreas Färber (9):
  dt-bindings: interrupt-controller: Add Realtek RTD1195/RTD1295 mux
  irqchip: Add Realtek RTD1295 mux driver
  irqchip: rtd1195-mux: Implement irq_get_irqchip_state
  arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts
  irqchip: rtd1195-mux: Add RTD1195 definitions
  ARM: dts: rtd1195: Add irq muxes and UART interrupts
  dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395
  irqchip: rtd1195-mux: Add RTD1395 definitions
  arm64: dts: realtek: rtd139x: Add irq muxes and UART interrupts

 .../interrupt-controller/realtek,rtd1195-mux.yaml  |  55 +++
 arch/arm/boot/dts/rtd1195.dtsi                     |  20 +
 arch/arm64/boot/dts/realtek/rtd129x.dtsi           |  22 +
 arch/arm64/boot/dts/realtek/rtd139x.dtsi           |  22 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-rtd1195-mux.c                  | 512 +++++++++++++++++++++
 6 files changed, 632 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
 create mode 100644 drivers/irqchip/irq-rtd1195-mux.c

-- 
2.16.4

[PATCH v5 1/9] dt-bindings: interrupt-controller: Add Realtek RTD1195/RTD1295 mux

[Andreas Färber]

Add binding for Realtek RTD1295 and RTD1195 IRQ mux.

Acked-by: Rob Herring <robh@kernel.org>
[AF: Converted to YAML schema]
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5: Unchanged
 
 v3 -> v4:
 * Squashed RTD1195
 * Converted to YAML schema
 * Renamed file from realtek,rtd119x-mux to realtek,rtd1195-mux
 
 v2 -> v3:
 * Renamed non-iso irq mux to "misc" for clarity

 v1 -> v2:
 * Dropped reference to common interrupt.txt bindings (Rob)
 
 .../interrupt-controller/realtek,rtd1195-mux.yaml  | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
new file mode 100644
index 000000000000..5cf3a28cedba
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1195-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTD1195/1295 IRQ Mux Controller
+
+maintainers:
+  - Andreas Färber <afaerber@suse.de>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - realtek,rtd1195-misc-irq-mux
+      - realtek,rtd1195-iso-irq-mux
+      - realtek,rtd1295-misc-irq-mux
+      - realtek,rtd1295-iso-irq-mux
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: Specifies the interrupt line which is mux'ed.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - "#interrupt-cells"
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    interrupt-controller@98007000 {
+        compatible = "realtek,rtd1295-iso-irq-mux";
+        reg = <0x98007000 0x100>;
+        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+    };
+...
-- 
2.16.4

[PATCH v5 2/9] irqchip: Add Realtek RTD1295 mux driver

[Andreas Färber]

This irq mux driver implements the RTD1295 SoC's non-linear mapping
between status and enable bits.

Based in part on QNAP's arch/arm/mach-rtk119x/rtk_irq_mux.c and
Synology's drivers/irqchip/irq-rtk.c code.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Aleix Roca Nonell <kernelrocks@gmail.com>
Signed-off-by: James Tai <james.tai@realtek.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5:
 * Renamed enable/disable to unmask/mask (Marc)
 * Factored out ack (Marc)
 * Clear all interrupts just in case
 * Added and mapped WDOG_NMI
 * Suppress mapping NMIs and reserved bits (Marc)
 * Dropped mask checks in mask/unmask (Marc)
 * Dropped mask check in interrupt handler
 * Renamed misc bits by inserting MIS_ for consistency
 * Duplicate irq_chip into rtd1195_mux_data
 * Renamed irq_chip from long rtd1195-mux to iso/misc, tidying /proc/interrupts
 
 v3 -> v4:
 * Drop no-op .irq_set_affinity callback (Thomas)
 * Clear all interrupts (James)
 * Updated SPDX-License-identifier
 * Use tabular formatting (Thomas)
 * Adopt different braces style (Thomas)
 * Use raw_spinlock_t (Thomas)
 * Shortened callback from isr_to_scpu_int_en_mask to isr_to_int_en_mask (Thomas)
 * Fixed of_iomap() error handling to not use IS_ERR()
 * Don't mask unmapped NMIs by checking for a non-zero mask
 * Cache SCPU_INT_EN to avoid superfluous reads (Thomas)
 * Renamed functions and variables from rtd119x to rtd1195
 
 v2 -> v3:
 * Adopted spin_lock_irq{save,restore}() (Marc)
 * Adopted single-write masking (Marc)
 * Adopted misc compatible string
 * Introduced explicit bit mapping
 * Adopted looped processing of pending interrupts (Marc)
 * Replaced unmask implementation with UMSK_ISR write
 * Introduced enable/disable ops and dropped no longer needed UART0 quirk
 
 v1 -> v2:
 * Renamed struct fields to avoid ambiguity (Marc)
 * Refactored offset lookup to avoid per-compatible init functions
 * Inserted white lines to clarify balanced locking (Marc)
 * Dropped forwarding of set_affinity to GIC (Marc)
 * Added spinlocks for consistency (Marc)
 * Limited initialization quirk to iso mux
 * Fixed spinlock initialization (Andrew)
 
 drivers/irqchip/Makefile          |   1 +
 drivers/irqchip/irq-rtd1195-mux.c | 291 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 292 insertions(+)
 create mode 100644 drivers/irqchip/irq-rtd1195-mux.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e806dda690ea..d678881eebc8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o
 obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o
 obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
 obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
+obj-$(CONFIG_ARCH_REALTEK)		+= irq-rtd1195-mux.o
diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
new file mode 100644
index 000000000000..0e86973aafca
--- /dev/null
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek RTD1295 IRQ mux
+ *
+ * Copyright (c) 2017-2019 Andreas Färber
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+
+#define UMSK_ISR_WRITE_DATA	BIT(0)
+#define ISR_WRITE_DATA		BIT(0)
+
+struct rtd1195_irq_mux_info {
+	const char	*name;
+	unsigned int	isr_offset;
+	unsigned int	umsk_isr_offset;
+	unsigned int	scpu_int_en_offset;
+	const u32	*isr_to_int_en_mask;
+};
+
+#define SCPU_INT_EN_RSV_MASK	0
+#define SCPU_INT_EN_NMI_MASK	GENMASK(31, 0)
+
+struct rtd1195_irq_mux_data {
+	void __iomem				*reg_isr;
+	void __iomem				*reg_umsk_isr;
+	void __iomem				*reg_scpu_int_en;
+	const struct rtd1195_irq_mux_info	*info;
+	int					irq;
+	u32					scpu_int_en;
+	struct irq_chip				chip;
+	struct irq_domain			*domain;
+	raw_spinlock_t				lock;
+};
+
+static void rtd1195_mux_irq_handle(struct irq_desc *desc)
+{
+	struct rtd1195_irq_mux_data *mux = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	u32 isr;
+	int i;
+
+	chained_irq_enter(chip, desc);
+
+	isr = readl_relaxed(mux->reg_isr);
+
+	while (isr) {
+		i = __ffs(isr);
+		isr &= ~BIT(i);
+
+		generic_handle_irq(irq_find_mapping(mux->domain, i));
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static void rtd1195_mux_ack_irq(struct irq_data *data)
+{
+	struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data);
+
+	writel_relaxed(BIT(data->hwirq) & ~ISR_WRITE_DATA, mux->reg_isr);
+}
+
+static void rtd1195_mux_mask_irq(struct irq_data *data)
+{
+	struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data);
+	u32 mask = mux->info->isr_to_int_en_mask[data->hwirq];
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&mux->lock, flags);
+
+	mux->scpu_int_en &= ~mask;
+	writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en);
+
+	raw_spin_unlock_irqrestore(&mux->lock, flags);
+}
+
+static void rtd1195_mux_unmask_irq(struct irq_data *data)
+{
+	struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data);
+	u32 mask = mux->info->isr_to_int_en_mask[data->hwirq];
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&mux->lock, flags);
+
+	mux->scpu_int_en |= mask;
+	writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en);
+
+	raw_spin_unlock_irqrestore(&mux->lock, flags);
+}
+
+static const struct irq_chip rtd1195_mux_irq_chip = {
+	.irq_ack		= rtd1195_mux_ack_irq,
+	.irq_mask		= rtd1195_mux_mask_irq,
+	.irq_unmask		= rtd1195_mux_unmask_irq,
+};
+
+static int rtd1195_mux_irq_domain_map(struct irq_domain *d,
+		unsigned int irq, irq_hw_number_t hw)
+{
+	struct rtd1195_irq_mux_data *mux = d->host_data;
+	u32 mask;
+
+	if (BIT(hw) == ISR_WRITE_DATA)
+		return -EINVAL;
+
+	mask = mux->info->isr_to_int_en_mask[hw];
+	if (mask == SCPU_INT_EN_RSV_MASK)
+		return -EINVAL;
+
+	if (mask == SCPU_INT_EN_NMI_MASK)
+		return -ENOTSUPP;
+
+	irq_set_chip_and_handler(irq, &mux->chip, handle_level_irq);
+	irq_set_chip_data(irq, mux);
+	irq_set_probe(irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = {
+	.xlate	= irq_domain_xlate_onecell,
+	.map	= rtd1195_mux_irq_domain_map,
+};
+
+enum rtd1295_iso_isr_bits {
+	RTD1295_ISO_ISR_UR0_SHIFT		= 2,
+	RTD1295_ISO_ISR_IRDA_SHIFT		= 5,
+	RTD1295_ISO_ISR_I2C0_SHIFT		= 8,
+	RTD1295_ISO_ISR_I2C1_SHIFT		= 11,
+	RTD1295_ISO_ISR_RTC_HSEC_SHIFT		= 12,
+	RTD1295_ISO_ISR_RTC_ALARM_SHIFT		= 13,
+	RTD1295_ISO_ISR_GPIOA_SHIFT		= 19,
+	RTD1295_ISO_ISR_GPIODA_SHIFT		= 20,
+	RTD1295_ISO_ISR_GPHY_DV_SHIFT		= 29,
+	RTD1295_ISO_ISR_GPHY_AV_SHIFT		= 30,
+	RTD1295_ISO_ISR_I2C1_REQ_SHIFT		= 31,
+};
+
+static const u32 rtd1295_iso_isr_to_scpu_int_en_mask[32] = {
+	[RTD1295_ISO_ISR_UR0_SHIFT]		= BIT(2),
+	[RTD1295_ISO_ISR_IRDA_SHIFT]		= BIT(5),
+	[RTD1295_ISO_ISR_I2C0_SHIFT]		= BIT(8),
+	[RTD1295_ISO_ISR_I2C1_SHIFT]		= BIT(11),
+	[RTD1295_ISO_ISR_RTC_HSEC_SHIFT]	= BIT(12),
+	[RTD1295_ISO_ISR_RTC_ALARM_SHIFT]	= BIT(13),
+	[RTD1295_ISO_ISR_GPIOA_SHIFT]		= BIT(19),
+	[RTD1295_ISO_ISR_GPIODA_SHIFT]		= BIT(20),
+	[RTD1295_ISO_ISR_GPHY_DV_SHIFT]		= BIT(29),
+	[RTD1295_ISO_ISR_GPHY_AV_SHIFT]		= BIT(30),
+	[RTD1295_ISO_ISR_I2C1_REQ_SHIFT]	= BIT(31),
+};
+
+enum rtd1295_misc_isr_bits {
+	RTD1295_MIS_ISR_WDOG_NMI_SHIFT		= 2,
+	RTD1295_MIS_ISR_UR1_SHIFT		= 3,
+	RTD1295_MIS_ISR_UR1_TO_SHIFT		= 5,
+	RTD1295_MIS_ISR_UR2_SHIFT		= 8,
+	RTD1295_MIS_ISR_RTC_MIN_SHIFT		= 10,
+	RTD1295_MIS_ISR_RTC_HOUR_SHIFT		= 11,
+	RTD1295_MIS_ISR_RTC_DATA_SHIFT		= 12,
+	RTD1295_MIS_ISR_UR2_TO_SHIFT		= 13,
+	RTD1295_MIS_ISR_I2C5_SHIFT		= 14,
+	RTD1295_MIS_ISR_I2C4_SHIFT		= 15,
+	RTD1295_MIS_ISR_GPIOA_SHIFT		= 19,
+	RTD1295_MIS_ISR_GPIODA_SHIFT		= 20,
+	RTD1295_MIS_ISR_LSADC0_SHIFT		= 21,
+	RTD1295_MIS_ISR_LSADC1_SHIFT		= 22,
+	RTD1295_MIS_ISR_I2C3_SHIFT		= 23,
+	RTD1295_MIS_ISR_SC0_SHIFT		= 24,
+	RTD1295_MIS_ISR_I2C2_SHIFT		= 26,
+	RTD1295_MIS_ISR_GSPI_SHIFT		= 27,
+	RTD1295_MIS_ISR_FAN_SHIFT		= 29,
+};
+
+static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = {
+	[RTD1295_MIS_ISR_UR1_SHIFT]		= BIT(3),
+	[RTD1295_MIS_ISR_UR1_TO_SHIFT]		= BIT(5),
+	[RTD1295_MIS_ISR_UR2_TO_SHIFT]		= BIT(6),
+	[RTD1295_MIS_ISR_UR2_SHIFT]		= BIT(7),
+	[RTD1295_MIS_ISR_RTC_MIN_SHIFT]		= BIT(10),
+	[RTD1295_MIS_ISR_RTC_HOUR_SHIFT]	= BIT(11),
+	[RTD1295_MIS_ISR_RTC_DATA_SHIFT]	= BIT(12),
+	[RTD1295_MIS_ISR_I2C5_SHIFT]		= BIT(14),
+	[RTD1295_MIS_ISR_I2C4_SHIFT]		= BIT(15),
+	[RTD1295_MIS_ISR_GPIOA_SHIFT]		= BIT(19),
+	[RTD1295_MIS_ISR_GPIODA_SHIFT]		= BIT(20),
+	[RTD1295_MIS_ISR_LSADC0_SHIFT]		= BIT(21),
+	[RTD1295_MIS_ISR_LSADC1_SHIFT]		= BIT(22),
+	[RTD1295_MIS_ISR_SC0_SHIFT]		= BIT(24),
+	[RTD1295_MIS_ISR_I2C2_SHIFT]		= BIT(26),
+	[RTD1295_MIS_ISR_GSPI_SHIFT]		= BIT(27),
+	[RTD1295_MIS_ISR_I2C3_SHIFT]		= BIT(28),
+	[RTD1295_MIS_ISR_FAN_SHIFT]		= BIT(29),
+	[RTD1295_MIS_ISR_WDOG_NMI_SHIFT]	= SCPU_INT_EN_NMI_MASK,
+};
+
+static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
+	.name			= "iso",
+	.isr_offset		= 0x0,
+	.umsk_isr_offset	= 0x4,
+	.scpu_int_en_offset	= 0x40,
+	.isr_to_int_en_mask	= rtd1295_iso_isr_to_scpu_int_en_mask,
+};
+
+static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
+	.name			= "misc",
+	.umsk_isr_offset	= 0x8,
+	.isr_offset		= 0xc,
+	.scpu_int_en_offset	= 0x80,
+	.isr_to_int_en_mask	= rtd1295_misc_isr_to_scpu_int_en_mask,
+};
+
+static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
+	{
+		.compatible = "realtek,rtd1295-iso-irq-mux",
+		.data = &rtd1295_iso_irq_mux_info,
+	},
+	{
+		.compatible = "realtek,rtd1295-misc-irq-mux",
+		.data = &rtd1295_misc_irq_mux_info,
+	},
+	{
+	}
+};
+
+static int __init rtd1195_irq_mux_init(struct device_node *node,
+				       struct device_node *parent)
+{
+	struct rtd1195_irq_mux_data *mux;
+	const struct of_device_id *match;
+	const struct rtd1195_irq_mux_info *info;
+	void __iomem *base;
+
+	match = of_match_node(rtd1295_irq_mux_dt_matches, node);
+	if (!match)
+		return -EINVAL;
+
+	info = match->data;
+	if (!info)
+		return -EINVAL;
+
+	base = of_iomap(node, 0);
+	if (!base)
+		return -EIO;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return -ENOMEM;
+
+	mux->info		= info;
+	mux->reg_isr		= base + info->isr_offset;
+	mux->reg_umsk_isr	= base + info->umsk_isr_offset;
+	mux->reg_scpu_int_en	= base + info->scpu_int_en_offset;
+	mux->chip		= rtd1195_mux_irq_chip;
+	mux->chip.name		= info->name;
+
+	mux->irq = irq_of_parse_and_map(node, 0);
+	if (mux->irq <= 0) {
+		kfree(mux);
+		return -EINVAL;
+	}
+
+	raw_spin_lock_init(&mux->lock);
+
+	/* Disable (mask) all interrupts */
+	writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en);
+
+	/* Ack (clear) all interrupts - not all are in UMSK_ISR, so use ISR */
+	writel_relaxed(~ISR_WRITE_DATA, mux->reg_isr);
+
+	mux->domain = irq_domain_add_linear(node, 32,
+				&rtd1195_mux_irq_domain_ops, mux);
+	if (!mux->domain) {
+		kfree(mux);
+		return -ENOMEM;
+	}
+
+	irq_set_chained_handler_and_data(mux->irq, rtd1195_mux_irq_handle, mux);
+
+	return 0;
+}
+IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);
-- 
2.16.4

[PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state

[Andreas Färber]

Implement the .irq_get_irqchip_state callback to retrieve pending,
active and masked interrupt status.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v5: New
 
 drivers/irqchip/irq-rtd1195-mux.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index 0e86973aafca..2f1bcfd9d5d6 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -7,6 +7,7 @@
 
 #include <linux/bitops.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
@@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct irq_data *data)
 	raw_spin_unlock_irqrestore(&mux->lock, flags);
 }
 
+static int rtd1195_mux_get_irqchip_state(struct irq_data *data,
+	enum irqchip_irq_state which, bool *state)
+{
+	struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data);
+	u32 val;
+
+	switch (which) {
+	case IRQCHIP_STATE_PENDING:
+		/*
+		 * UMSK_ISR provides the unmasked pending interrupts,
+		 * except UART and I2C.
+		 */
+		val = readl_relaxed(mux->reg_umsk_isr);
+		*state = !!(val & BIT(data->hwirq));
+		break;
+	case IRQCHIP_STATE_ACTIVE:
+		/*
+		 * ISR provides the masked pending interrupts,
+		 * including UART and I2C.
+		 */
+		val = readl_relaxed(mux->reg_isr);
+		*state = !!(val & BIT(data->hwirq));
+		break;
+	case IRQCHIP_STATE_MASKED:
+		val = mux->info->isr_to_int_en_mask[data->hwirq];
+		*state = !(mux->scpu_int_en & val);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct irq_chip rtd1195_mux_irq_chip = {
 	.irq_ack		= rtd1195_mux_ack_irq,
 	.irq_mask		= rtd1195_mux_mask_irq,
 	.irq_unmask		= rtd1195_mux_unmask_irq,
+	.irq_get_irqchip_state	= rtd1195_mux_get_irqchip_state,
 };
 
 static int rtd1195_mux_irq_domain_map(struct irq_domain *d,
-- 
2.16.4

[PATCH v5 4/9] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts

[Andreas Färber]

Add iso and misc IRQ mux DT nodes to RTD129x SoC family.

Update the UART DT nodes with interrupts from these muxes,
so that UART0 can be used without earlycon.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5: Unchanged
 
 v3 -> v4:
 * Rebased onto chip-info and r-bus
 * Dropped schema-violating second interrupts for UART1 and UART2
 
 v2 -> v3:
 * Added nodes to rtd129x.dtsi instead of rtd1295.dtsi
 * Adopted misc compatible string
 * Renamed node label from irq_mux to misc_irq_mux for clarity
 
 v1 -> v2:
 * Rebased
 
 arch/arm64/boot/dts/realtek/rtd129x.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
index 7d56c9f5d48a..188b4f256917 100644
--- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
@@ -86,6 +86,14 @@
 				#reset-cells = <1>;
 			};
 
+			iso_irq_mux: interrupt-controller@7000 {
+				compatible = "realtek,rtd1295-iso-irq-mux";
+				reg = <0x7000 0x100>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			iso_reset: reset-controller@7088 {
 				compatible = "snps,dw-low-reset";
 				reg = <0x7088 0x4>;
@@ -105,6 +113,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <27000000>;
 				resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+				interrupt-parent = <&iso_irq_mux>;
+				interrupts = <2>;
 				status = "disabled";
 			};
 
@@ -115,6 +125,14 @@
 				      <0x171d8 0x4>;
 			};
 
+			misc_irq_mux: interrupt-controller@1b000 {
+				compatible = "realtek,rtd1295-misc-irq-mux";
+				reg = <0x1b000 0x100>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			uart1: serial@1b200 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x1b200 0x100>;
@@ -122,6 +140,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <432000000>;
 				resets = <&reset2 RTD1295_RSTN_UR1>;
+				interrupt-parent = <&misc_irq_mux>;
+				interrupts = <3>;
 				status = "disabled";
 			};
 
@@ -132,6 +152,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <432000000>;
 				resets = <&reset2 RTD1295_RSTN_UR2>;
+				interrupt-parent = <&misc_irq_mux>;
+				interrupts = <8>;
 				status = "disabled";
 			};
 		};
-- 
2.16.4

[PATCH v5 5/9] irqchip: rtd1195-mux: Add RTD1195 definitions

[Andreas Färber]

Add compatible strings and bit mappings for Realtek RTD1195 SoC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5:
 * Mapped WDOG_NMI
 * Filled in irq_chip names
 
 v3 -> v4:
 * Use tabular formatting (Thomas)
 * Adopt different braces style (Thomas)
 * Updated with shortened isr_to_int_en_mask callback name (Thomas)
 * Renamed functions and variables from rtd119x_ to rtd1195_
 * Renamed enum values from RTD119X_ to RTD1195_
 
 v3: New
 
 drivers/irqchip/irq-rtd1195-mux.c | 104 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 103 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index 2f1bcfd9d5d6..e3e2e42d9df2 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Realtek RTD1295 IRQ mux
+ * Realtek RTD1195/RTD1295 IRQ mux
  *
  * Copyright (c) 2017-2019 Andreas Färber
  */
@@ -166,6 +166,82 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = {
 	.map	= rtd1195_mux_irq_domain_map,
 };
 
+enum rtd1195_iso_isr_bits {
+	RTD1195_ISO_ISR_TC3_SHIFT		= 1,
+	RTD1195_ISO_ISR_UR0_SHIFT		= 2,
+	RTD1195_ISO_ISR_IRDA_SHIFT		= 5,
+	RTD1195_ISO_ISR_WDOG_NMI_SHIFT		= 7,
+	RTD1195_ISO_ISR_I2C0_SHIFT		= 8,
+	RTD1195_ISO_ISR_TC4_SHIFT		= 9,
+	RTD1195_ISO_ISR_I2C6_SHIFT		= 10,
+	RTD1195_ISO_ISR_RTC_HSEC_SHIFT		= 12,
+	RTD1195_ISO_ISR_RTC_ALARM_SHIFT		= 13,
+	RTD1195_ISO_ISR_VFD_WDONE_SHIFT		= 14,
+	RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT	= 15,
+	RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT	= 16,
+	RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT	= 17,
+	RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT	= 18,
+	RTD1195_ISO_ISR_GPIOA_SHIFT		= 19,
+	RTD1195_ISO_ISR_GPIODA_SHIFT		= 20,
+	RTD1195_ISO_ISR_CEC_SHIFT		= 22,
+};
+
+static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = {
+	[RTD1195_ISO_ISR_UR0_SHIFT]		= BIT(2),
+	[RTD1195_ISO_ISR_IRDA_SHIFT]		= BIT(5),
+	[RTD1195_ISO_ISR_I2C0_SHIFT]		= BIT(8),
+	[RTD1195_ISO_ISR_I2C6_SHIFT]		= BIT(10),
+	[RTD1195_ISO_ISR_RTC_HSEC_SHIFT]	= BIT(12),
+	[RTD1195_ISO_ISR_RTC_ALARM_SHIFT]	= BIT(13),
+	[RTD1195_ISO_ISR_VFD_WDONE_SHIFT]	= BIT(14),
+	[RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT]	= BIT(15),
+	[RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT]	= BIT(16),
+	[RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT]	= BIT(17),
+	[RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT]	= BIT(18),
+	[RTD1195_ISO_ISR_GPIOA_SHIFT]		= BIT(19),
+	[RTD1195_ISO_ISR_GPIODA_SHIFT]		= BIT(20),
+	[RTD1195_ISO_ISR_CEC_SHIFT]		= BIT(22),
+};
+
+enum rtd1195_misc_isr_bits {
+	RTD1195_MIS_ISR_WDOG_NMI_SHIFT		= 2,
+	RTD1195_MIS_ISR_UR1_SHIFT		= 3,
+	RTD1195_MIS_ISR_I2C1_SHIFT		= 4,
+	RTD1195_MIS_ISR_UR1_TO_SHIFT		= 5,
+	RTD1195_MIS_ISR_TC0_SHIFT		= 6,
+	RTD1195_MIS_ISR_TC1_SHIFT		= 7,
+	RTD1195_MIS_ISR_RTC_HSEC_SHIFT		= 9,
+	RTD1195_MIS_ISR_RTC_MIN_SHIFT		= 10,
+	RTD1195_MIS_ISR_RTC_HOUR_SHIFT		= 11,
+	RTD1195_MIS_ISR_RTC_DATE_SHIFT		= 12,
+	RTD1195_MIS_ISR_I2C5_SHIFT		= 14,
+	RTD1195_MIS_ISR_I2C4_SHIFT		= 15,
+	RTD1195_MIS_ISR_GPIOA_SHIFT		= 19,
+	RTD1195_MIS_ISR_GPIODA_SHIFT		= 20,
+	RTD1195_MIS_ISR_LSADC_SHIFT		= 21,
+	RTD1195_MIS_ISR_I2C3_SHIFT		= 23,
+	RTD1195_MIS_ISR_I2C2_SHIFT		= 26,
+	RTD1195_MIS_ISR_GSPI_SHIFT		= 27,
+};
+
+static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = {
+	[RTD1195_MIS_ISR_UR1_SHIFT]		= BIT(3),
+	[RTD1195_MIS_ISR_I2C1_SHIFT]		= BIT(4),
+	[RTD1195_MIS_ISR_UR1_TO_SHIFT]		= BIT(5),
+	[RTD1195_MIS_ISR_RTC_MIN_SHIFT]		= BIT(10),
+	[RTD1195_MIS_ISR_RTC_HOUR_SHIFT]	= BIT(11),
+	[RTD1195_MIS_ISR_RTC_DATE_SHIFT]	= BIT(12),
+	[RTD1195_MIS_ISR_I2C5_SHIFT]		= BIT(14),
+	[RTD1195_MIS_ISR_I2C4_SHIFT]		= BIT(15),
+	[RTD1195_MIS_ISR_GPIOA_SHIFT]		= BIT(19),
+	[RTD1195_MIS_ISR_GPIODA_SHIFT]		= BIT(20),
+	[RTD1195_MIS_ISR_LSADC_SHIFT]		= BIT(21),
+	[RTD1195_MIS_ISR_I2C2_SHIFT]		= BIT(26),
+	[RTD1195_MIS_ISR_GSPI_SHIFT]		= BIT(27),
+	[RTD1195_MIS_ISR_I2C3_SHIFT]		= BIT(28),
+	[RTD1195_MIS_ISR_WDOG_NMI_SHIFT]	= SCPU_INT_EN_NMI_MASK,
+};
+
 enum rtd1295_iso_isr_bits {
 	RTD1295_ISO_ISR_UR0_SHIFT		= 2,
 	RTD1295_ISO_ISR_IRDA_SHIFT		= 5,
@@ -238,6 +314,14 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = {
 	[RTD1295_MIS_ISR_WDOG_NMI_SHIFT]	= SCPU_INT_EN_NMI_MASK,
 };
 
+static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = {
+	.name			= "iso",
+	.isr_offset		= 0x0,
+	.umsk_isr_offset	= 0x4,
+	.scpu_int_en_offset	= 0x40,
+	.isr_to_int_en_mask	= rtd1195_iso_isr_to_scpu_int_en_mask,
+};
+
 static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
 	.name			= "iso",
 	.isr_offset		= 0x0,
@@ -246,6 +330,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
 	.isr_to_int_en_mask	= rtd1295_iso_isr_to_scpu_int_en_mask,
 };
 
+static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = {
+	.name			= "misc",
+	.umsk_isr_offset	= 0x8,
+	.isr_offset		= 0xc,
+	.scpu_int_en_offset	= 0x80,
+	.isr_to_int_en_mask	= rtd1195_misc_isr_to_scpu_int_en_mask,
+};
+
 static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
 	.name			= "misc",
 	.umsk_isr_offset	= 0x8,
@@ -255,10 +347,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
 };
 
 static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
+	{
+		.compatible = "realtek,rtd1195-iso-irq-mux",
+		.data = &rtd1195_iso_irq_mux_info,
+	},
 	{
 		.compatible = "realtek,rtd1295-iso-irq-mux",
 		.data = &rtd1295_iso_irq_mux_info,
 	},
+	{
+		.compatible = "realtek,rtd1195-misc-irq-mux",
+		.data = &rtd1195_misc_irq_mux_info,
+	},
 	{
 		.compatible = "realtek,rtd1295-misc-irq-mux",
 		.data = &rtd1295_misc_irq_mux_info,
@@ -323,5 +423,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node,
 
 	return 0;
 }
+IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init);
 IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init);
 IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);
-- 
2.16.4

[PATCH v5 6/9] ARM: dts: rtd1195: Add irq muxes and UART interrupts

[Andreas Färber]

Add iso and misc IRQ mux DT nodes for the Realtek RTD1195 SoC.

Update the UART DT nodes with interrupts from those muxes,
so that UART0 can be used without earlycon.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5: Unchanged
 
 v4: New
 
 arch/arm/boot/dts/rtd1195.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
index db1171c5adfa..ee7761ae4ee0 100644
--- a/arch/arm/boot/dts/rtd1195.dtsi
+++ b/arch/arm/boot/dts/rtd1195.dtsi
@@ -118,6 +118,14 @@
 				#reset-cells = <1>;
 			};
 
+			iso_irq_mux: interrupt-controller@7000 {
+				compatible = "realtek,rtd1195-iso-irq-mux";
+				reg = <0x7000 0x100>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			iso_reset: reset-controller@7088 {
 				compatible = "snps,dw-low-reset";
 				reg = <0x7088 0x4>;
@@ -137,6 +145,8 @@
 				reg-io-width = <4>;
 				resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
 				clock-frequency = <27000000>;
+				interrupt-parent = <&iso_irq_mux>;
+				interrupts = <2>;
 				status = "disabled";
 			};
 
@@ -145,6 +155,14 @@
 				reg = <0x1a200 0x8>;
 			};
 
+			misc_irq_mux: interrupt-controller@1b000 {
+				compatible = "realtek,rtd1195-misc-irq-mux";
+				reg = <0x1b000 0x100>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			uart1: serial@1b200 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x1b200 0x100>;
@@ -152,6 +170,8 @@
 				reg-io-width = <4>;
 				resets = <&reset2 RTD1195_RSTN_UR1>;
 				clock-frequency = <27000000>;
+				interrupt-parent = <&misc_irq_mux>;
+				interrupts = <3>;
 				status = "disabled";
 			};
 		};
-- 
2.16.4

[PATCH v5 7/9] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395

[Andreas Färber]

Add compatible strings for Realtek RTD1395 SoC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5: Unchanged
 
 v4: New
 
 .../devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml   | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
index 5cf3a28cedba..7c2a31548d46 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml
@@ -19,6 +19,8 @@ properties:
       - realtek,rtd1195-iso-irq-mux
       - realtek,rtd1295-misc-irq-mux
       - realtek,rtd1295-iso-irq-mux
+      - realtek,rtd1395-misc-irq-mux
+      - realtek,rtd1395-iso-irq-mux
 
   reg:
     maxItems: 1
-- 
2.16.4

[PATCH v5 8/9] irqchip: rtd1195-mux: Add RTD1395 definitions

[Andreas Färber]

Add compatible strings and bit mappings for Realtek RTD1395 SoC.

Based on BPI-M4-bsp linux-rtk/drivers/irqchip/irq-rtd139x.h.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 @Realtek: Does RTD1395 still have the WDOG_NMI misc interrupt at bit 2?
 
 v4 -> v5:
 * Renamed misc bits from MISC_ to MIS_ for consistency
 * Filled in irq_chip names
 
 v4: New
 
 drivers/irqchip/irq-rtd1195-mux.c | 85 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 84 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index e3e2e42d9df2..e0264759c0a8 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Realtek RTD1195/RTD1295 IRQ mux
+ * Realtek RTD1195/RTD1295/RTD1395 IRQ mux
  *
+ * Copyright (C) 2017 Realtek Semiconductor Corporation
  * Copyright (c) 2017-2019 Andreas Färber
  */
 
@@ -314,6 +315,62 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = {
 	[RTD1295_MIS_ISR_WDOG_NMI_SHIFT]	= SCPU_INT_EN_NMI_MASK,
 };
 
+enum rtd1395_iso_isr_bits {
+	RTD1395_ISO_ISR_UR0_SHIFT		= 2,
+	RTD1395_ISO_ISR_IRDA_SHIFT		= 5,
+	RTD1395_ISO_ISR_I2C0_SHIFT		= 8,
+	RTD1395_ISO_ISR_I2C1_SHIFT		= 11,
+	RTD1395_ISO_ISR_RTC_HSEC_SHIFT		= 12,
+	RTD1395_ISO_ISR_RTC_ALARM_SHIFT		= 13,
+	RTD1395_ISO_ISR_LSADC0_SHIFT		= 16,
+	RTD1395_ISO_ISR_LSADC1_SHIFT		= 17,
+	RTD1395_ISO_ISR_GPIOA_SHIFT		= 19,
+	RTD1395_ISO_ISR_GPIODA_SHIFT		= 20,
+	RTD1395_ISO_ISR_GPHY_HV_SHIFT		= 28,
+	RTD1395_ISO_ISR_GPHY_DV_SHIFT		= 29,
+	RTD1395_ISO_ISR_GPHY_AV_SHIFT		= 30,
+	RTD1395_ISO_ISR_I2C1_REQ_SHIFT		= 31,
+};
+
+static const u32 rtd1395_iso_isr_to_scpu_int_en_mask[32] = {
+	[RTD1395_ISO_ISR_UR0_SHIFT]		= BIT(2),
+	[RTD1395_ISO_ISR_IRDA_SHIFT]		= BIT(5),
+	[RTD1395_ISO_ISR_I2C0_SHIFT]		= BIT(8),
+	[RTD1395_ISO_ISR_I2C1_SHIFT]		= BIT(11),
+	[RTD1395_ISO_ISR_RTC_HSEC_SHIFT]	= BIT(12),
+	[RTD1395_ISO_ISR_RTC_ALARM_SHIFT]	= BIT(13),
+	[RTD1395_ISO_ISR_LSADC0_SHIFT]		= BIT(16),
+	[RTD1395_ISO_ISR_LSADC1_SHIFT]		= BIT(17),
+	[RTD1395_ISO_ISR_GPIOA_SHIFT]		= BIT(19),
+	[RTD1395_ISO_ISR_GPIODA_SHIFT]		= BIT(20),
+	[RTD1395_ISO_ISR_GPHY_HV_SHIFT]		= BIT(28),
+	[RTD1395_ISO_ISR_GPHY_DV_SHIFT]		= BIT(29),
+	[RTD1395_ISO_ISR_GPHY_AV_SHIFT]		= BIT(30),
+	[RTD1395_ISO_ISR_I2C1_REQ_SHIFT]	= BIT(31),
+};
+
+enum rtd1395_misc_isr_bits {
+	RTD1395_MIS_ISR_UR1_SHIFT		= 3,
+	RTD1395_MIS_ISR_UR1_TO_SHIFT		= 5,
+	RTD1395_MIS_ISR_UR2_SHIFT		= 8,
+	RTD1395_MIS_ISR_UR2_TO_SHIFT		= 13,
+	RTD1395_MIS_ISR_I2C5_SHIFT		= 14,
+	RTD1395_MIS_ISR_SC0_SHIFT		= 24,
+	RTD1395_MIS_ISR_SPI_SHIFT		= 27,
+	RTD1395_MIS_ISR_FAN_SHIFT		= 29,
+};
+
+static const u32 rtd1395_misc_isr_to_scpu_int_en_mask[32] = {
+	[RTD1395_MIS_ISR_UR1_SHIFT]		= BIT(3),
+	[RTD1395_MIS_ISR_UR1_TO_SHIFT]		= BIT(5),
+	[RTD1395_MIS_ISR_UR2_TO_SHIFT]		= BIT(6),
+	[RTD1395_MIS_ISR_UR2_SHIFT]		= BIT(7),
+	[RTD1395_MIS_ISR_I2C5_SHIFT]		= BIT(14),
+	[RTD1395_MIS_ISR_SC0_SHIFT]		= BIT(24),
+	[RTD1395_MIS_ISR_SPI_SHIFT]		= BIT(27),
+	[RTD1395_MIS_ISR_FAN_SHIFT]		= BIT(29),
+};
+
 static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = {
 	.name			= "iso",
 	.isr_offset		= 0x0,
@@ -330,6 +387,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = {
 	.isr_to_int_en_mask	= rtd1295_iso_isr_to_scpu_int_en_mask,
 };
 
+static const struct rtd1195_irq_mux_info rtd1395_iso_irq_mux_info = {
+	.name			= "iso",
+	.isr_offset		= 0x0,
+	.umsk_isr_offset	= 0x4,
+	.scpu_int_en_offset	= 0x40,
+	.isr_to_int_en_mask	= rtd1395_iso_isr_to_scpu_int_en_mask,
+};
+
 static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = {
 	.name			= "misc",
 	.umsk_isr_offset	= 0x8,
@@ -346,6 +411,14 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = {
 	.isr_to_int_en_mask	= rtd1295_misc_isr_to_scpu_int_en_mask,
 };
 
+static const struct rtd1195_irq_mux_info rtd1395_misc_irq_mux_info = {
+	.name			= "misc",
+	.umsk_isr_offset	= 0x8,
+	.isr_offset		= 0xc,
+	.scpu_int_en_offset	= 0x80,
+	.isr_to_int_en_mask	= rtd1395_misc_isr_to_scpu_int_en_mask,
+};
+
 static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
 	{
 		.compatible = "realtek,rtd1195-iso-irq-mux",
@@ -355,6 +428,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
 		.compatible = "realtek,rtd1295-iso-irq-mux",
 		.data = &rtd1295_iso_irq_mux_info,
 	},
+	{
+		.compatible = "realtek,rtd1395-iso-irq-mux",
+		.data = &rtd1395_iso_irq_mux_info,
+	},
 	{
 		.compatible = "realtek,rtd1195-misc-irq-mux",
 		.data = &rtd1195_misc_irq_mux_info,
@@ -363,6 +440,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = {
 		.compatible = "realtek,rtd1295-misc-irq-mux",
 		.data = &rtd1295_misc_irq_mux_info,
 	},
+	{
+		.compatible = "realtek,rtd1395-misc-irq-mux",
+		.data = &rtd1395_misc_irq_mux_info,
+	},
 	{
 	}
 };
@@ -425,5 +506,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node,
 }
 IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init);
 IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1395_iso_mux, "realtek,rtd1395-iso-irq-mux", rtd1195_irq_mux_init);
 IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init);
 IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);
+IRQCHIP_DECLARE(rtd1395_misc_mux, "realtek,rtd1395-misc-irq-mux", rtd1195_irq_mux_init);
-- 
2.16.4

[PATCH v5 9/9] arm64: dts: realtek: rtd139x: Add irq muxes and UART interrupts

[Andreas Färber]

Add iso and misc IRQ mux DT nodes for Realtek RTD1395 SoC.

Update the UART DT nodes with interrupts from these muxes,
so that UART0 can be used without earlycon.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v4 -> v5: Unchanged
 
 v4: New
 
 arch/arm64/boot/dts/realtek/rtd139x.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
index 706da12f9ea3..f53cb8a5083b 100644
--- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
@@ -84,6 +84,14 @@
 				#reset-cells = <1>;
 			};
 
+			iso_irq_mux: interrupt-controller@7000 {
+				compatible = "realtek,rtd1395-iso-irq-mux";
+				reg = <0x7000 0x100>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			iso_reset: reset-controller@7088 {
 				compatible = "snps,dw-low-reset";
 				reg = <0x7088 0x4>;
@@ -103,6 +111,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <27000000>;
 				resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+				interrupt-parent = <&iso_irq_mux>;
+				interrupts = <2>;
 				status = "disabled";
 			};
 
@@ -111,6 +121,14 @@
 				reg = <0x1a200 0x8>;
 			};
 
+			misc_irq_mux: interrupt-controller@1b000 {
+				compatible = "realtek,rtd1395-misc-irq-mux";
+				reg = <0x1b000 0x100>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
 			uart1: serial@1b200 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x1b200 0x100>;
@@ -118,6 +136,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <432000000>;
 				resets = <&reset2 RTD1295_RSTN_UR1>;
+				interrupt-parent = <&misc_irq_mux>;
+				interrupts = <3>;
 				status = "disabled";
 			};
 
@@ -128,6 +148,8 @@
 				reg-io-width = <4>;
 				clock-frequency = <432000000>;
 				resets = <&reset2 RTD1295_RSTN_UR2>;
+				interrupt-parent = <&misc_irq_mux>;
+				interrupts = <8>;
 				status = "disabled";
 			};
 		};
-- 
2.16.4

Re: [PATCH v5 7/9] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395

[Rob Herring]

On Thu, 21 Nov 2019 06:02:06 +0100, =?UTF-8?q?Andreas=20F=C3=A4rber?= wrote:
> Add compatible strings for Realtek RTD1395 SoC.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v4 -> v5: Unchanged
>  
>  v4: New
>  
>  .../devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml   | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state

[Marc Zyngier]

On 2019-11-21 05:02, Andreas Färber wrote:
> Implement the .irq_get_irqchip_state callback to retrieve pending,
> active and masked interrupt status.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v5: New
>
>  drivers/irqchip/irq-rtd1195-mux.c | 36 
> ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/drivers/irqchip/irq-rtd1195-mux.c
> b/drivers/irqchip/irq-rtd1195-mux.c
> index 0e86973aafca..2f1bcfd9d5d6 100644
> --- a/drivers/irqchip/irq-rtd1195-mux.c
> +++ b/drivers/irqchip/irq-rtd1195-mux.c
> @@ -7,6 +7,7 @@
>
>  #include <linux/bitops.h>
>  #include <linux/io.h>
> +#include <linux/interrupt.h>
>  #include <linux/irqchip.h>
>  #include <linux/irqchip/chained_irq.h>
>  #include <linux/irqdomain.h>
> @@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct 
> irq_data *data)
>  	raw_spin_unlock_irqrestore(&mux->lock, flags);
>  }
>
> +static int rtd1195_mux_get_irqchip_state(struct irq_data *data,
> +	enum irqchip_irq_state which, bool *state)
> +{
> +	struct rtd1195_irq_mux_data *mux = 
> irq_data_get_irq_chip_data(data);
> +	u32 val;
> +
> +	switch (which) {
> +	case IRQCHIP_STATE_PENDING:
> +		/*
> +		 * UMSK_ISR provides the unmasked pending interrupts,
> +		 * except UART and I2C.
> +		 */
> +		val = readl_relaxed(mux->reg_umsk_isr);
> +		*state = !!(val & BIT(data->hwirq));
> +		break;
> +	case IRQCHIP_STATE_ACTIVE:
> +		/*
> +		 * ISR provides the masked pending interrupts,
> +		 * including UART and I2C.
> +		 */
> +		val = readl_relaxed(mux->reg_isr);
> +		*state = !!(val & BIT(data->hwirq));
> +		break;

ACTIVE has a very specific meaning: it indicates that the interrupt is
being handled right now. What this tells you is whether the interrupt
is pending and unmasked, which is an entirely different thing.

This will lead to irq_disable() misbehaving (it will assume that
the interrupt is active while it is only pending).

Given what the HW exposes (or rather, what this driver exposes of the 
HW),
I don't think you can implement this state.

> +	case IRQCHIP_STATE_MASKED:
> +		val = mux->info->isr_to_int_en_mask[data->hwirq];
> +		*state = !(mux->scpu_int_en & val);

Shouldn't you take the corresponding spinlock given that you can
have a pending update in parallel?

         M.

> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static const struct irq_chip rtd1195_mux_irq_chip = {
>  	.irq_ack		= rtd1195_mux_ack_irq,
>  	.irq_mask		= rtd1195_mux_mask_irq,
>  	.irq_unmask		= rtd1195_mux_unmask_irq,
> +	.irq_get_irqchip_state	= rtd1195_mux_get_irqchip_state,
>  };
>
>  static int rtd1195_mux_irq_domain_map(struct irq_domain *d,

-- 
Jazz is not dead. It just smells funny...