From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0C42C432C0 for ; Sat, 23 Nov 2019 00:31:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C11692070E for ; Sat, 23 Nov 2019 00:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbfKWAbH (ORCPT ); Fri, 22 Nov 2019 19:31:07 -0500 Received: from mga03.intel.com ([134.134.136.65]:53943 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726089AbfKWAbH (ORCPT ); Fri, 22 Nov 2019 19:31:07 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2019 16:31:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,231,1571727600"; d="scan'208";a="382242622" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.68]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2019 16:30:56 -0800 Date: Fri, 22 Nov 2019 16:30:56 -0800 From: "Luck, Tony" To: Peter Zijlstra Cc: Ingo Molnar , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Ashok Raj , Ravi V Shankar , linux-kernel , x86 Subject: Re: [PATCH v10 6/6] x86/split_lock: Enable split lock detection by kernel parameter Message-ID: <20191123003056.GA28761@agluck-desk2.amr.corp.intel.com> References: <1574297603-198156-1-git-send-email-fenghua.yu@intel.com> <1574297603-198156-7-git-send-email-fenghua.yu@intel.com> <20191121060444.GA55272@gmail.com> <20191121130153.GS4097@hirez.programming.kicks-ass.net> <20191121171214.GD12042@gmail.com> <20191121173444.GA5581@agluck-desk2.amr.corp.intel.com> <20191122105141.GY4114@hirez.programming.kicks-ass.net> <20191122152715.GA1909@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122152715.GA1909@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 22, 2019 at 04:27:15PM +0100, Peter Zijlstra wrote: This all looks dubious on an HT system .... three snips from your patch: > +static bool __sld_msr_set(bool on) > +{ > + u64 test_ctrl_val; > + > + if (rdmsrl_safe(MSR_TEST_CTRL, test_ctrl_val)) > + return false; > + > + if (on) > + test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; > + else > + test_ctrl_val &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT; > + > + if (wrmsrl_safe(MSR_TEST_CTRL, test_ctrl_val)) > + return false; > + > + return true; > +} > +void switch_sld(struct task_struct *prev) > +{ > + __sld_set_msr(true); > + clear_tsk_thread_flag(current, TIF_CLD); > +} > @@ -654,6 +654,9 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) > /* Enforce MSR update to ensure consistent state */ > __speculation_ctrl_update(~tifn, tifn); > } > + > + if (tifp & _TIF_SLD) > + switch_sld(prev_p); > } Don't you have some horrible races between the two logical processors on the same core as they both try to set/clear the MSR that is shared at the core level? -Tony