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[70.5.93.147]) by smtp.gmail.com with ESMTPSA id m205sm2685802oib.27.2019.11.22.16.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2019 16:44:38 -0800 (PST) Date: Fri, 22 Nov 2019 18:44:36 -0600 From: Rob Herring To: Kalyan Thota Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, seanpaul@chromium.org, hoegsberg@chromium.org, dhar@codeaurora.org, jsanka@codeaurora.org, chandanu@codeaurora.org, travitej@codeaurora.org, nganji@codeaurora.org Subject: Re: [PATCH v3] msm:disp:dpu1: add support for display for SC7180 target Message-ID: <20191123004436.GA18110@bogus> References: <1574252368-4645-1-git-send-email-kalyan_t@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1574252368-4645-1-git-send-email-kalyan_t@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 20, 2019 at 05:49:28PM +0530, Kalyan Thota wrote: > Add display hw catalog changes for SC7180 target. > > Changes in v1: > - Configure register offsets and capabilities for the > display hw blocks. > > Changes in v2: > - mdss_irq data type has changed in the dependent > patch, accommodate the necessary changes. > - Add co-developed-by tags in the commit msg (Stephen Boyd). > > Changes in v3: > - fix kernel checkpatch errors in v2 But not the one telling you to split bindings to separate patch? > > This patch has dependency on the below series > > https://patchwork.kernel.org/patch/11253647/ > > Co-developed-by: Shubhashree Dhar > Signed-off-by: Shubhashree Dhar > Co-developed-by: Raviteja Tamatam > Signed-off-by: Raviteja Tamatam > Signed-off-by: Kalyan Thota > --- > .../devicetree/bindings/display/msm/dpu.txt | 4 +- Acked-by: Rob Herring > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++++++++++++++++++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > drivers/gpu/drm/msm/msm_drv.c | 4 +- > 6 files changed, 190 insertions(+), 15 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt > index a61dd40..512f022 100644 > --- a/Documentation/devicetree/bindings/display/msm/dpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt > @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC. > > MDSS: > Required properties: > -- compatible: "qcom,sdm845-mdss" > +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" > - reg: physical base address and length of contoller's registers. > - reg-names: register region names. The following region is required: > * "mdss" > @@ -41,7 +41,7 @@ Optional properties: > > MDP: > Required properties: > -- compatible: "qcom,sdm845-dpu" > +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" > - reg: physical base address and length of controller's registers. > - reg-names : register region names. The following region is required: > * "mdp"