From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17EA2C43215 for ; Fri, 29 Nov 2019 14:48:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E939F217AB for ; Fri, 29 Nov 2019 14:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727156AbfK2OsD (ORCPT ); Fri, 29 Nov 2019 09:48:03 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:44155 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726808AbfK2OsD (ORCPT ); Fri, 29 Nov 2019 09:48:03 -0500 Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 29 Nov 2019 22:47:48 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong CC: Jian Hu , Kevin Hilman , Rob Herring , Martin Blumenstingl , Michael Turquette , Stephen Boyd , Qiufang Dai , Jianxin Pan , Victor Wan , Chandle Zou , , , , Subject: [PATCH v3 7/7] arm64: dts: meson: add A1 PLL and periphs clock controller Date: Fri, 29 Nov 2019 22:46:05 +0800 Message-ID: <20191129144605.182774-8-jian.hu@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191129144605.182774-1-jian.hu@amlogic.com> References: <20191129144605.182774-1-jian.hu@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.25] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add A1 PLL and periphs clock controller node, there are parent clocks in periphs clocks for PLL clocks, and there are parent clocks in PLL clocks for periphs clocks. They rely on each other. Signed-off-by: Jian Hu --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 7210ad049d1d..ba1cb4aa594b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -5,6 +5,8 @@ #include #include +#include +#include / { compatible = "amlogic,a1"; @@ -74,6 +76,30 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + clkc_pll: pll-clock-controller { + compatible = "amlogic,a1-pll-clkc"; + #clock-cells = <1>; + reg = <0 0x7c80 0 0x21c>; + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, + <&clkc_periphs CLKID_XTAL_HIFIPLL>; + clock-names = "xtal_fixpll", "xtal_hifipll"; + }; + + clkc_periphs: periphs-clock-controller { + compatible = "amlogic,a1-periphs-clkc"; + #clock-cells = <1>; + reg = <0 0x800 0 0x104>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; + uart_AO: serial@1c00 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; -- 2.24.0