From: Jian Hu <jian.hu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: Jian Hu <jian.hu@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Rob Herring <robh@kernel.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>,
Chandle Zou <chandle.zou@amlogic.com>,
<linux-clk@vger.kernel.org>, <linux-amlogic@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v4 1/6] dt-bindings: clock: meson: add A1 PLL clock controller bindings
Date: Fri, 6 Dec 2019 15:40:47 +0800 [thread overview]
Message-ID: <20191206074052.15557-2-jian.hu@amlogic.com> (raw)
In-Reply-To: <20191206074052.15557-1-jian.hu@amlogic.com>
Add the documentation to support Amlogic A1 PLL clock driver,
and add A1 PLL clock controller bindings.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 59 +++++++++++++++++++
include/dt-bindings/clock/a1-pll-clkc.h | 16 +++++
2 files changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
new file mode 100644
index 000000000000..7feeef5abf1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@jian.hu.com>
+
+properties:
+ compatible:
+ - enum:
+ - amlogic,a1-pll-clkc
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+clocks:
+ minItems: 2
+ maxItems: 2
+ items:
+ - description: Input xtal_fixpll
+ - description: Input xtal_hifipll
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: xtal_fixpll
+ - const: xtal_hifipll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h
new file mode 100644
index 000000000000..58eae237e503
--- /dev/null
+++ b/include/dt-bindings/clock/a1-pll-clkc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_PLL_CLKC_H
+#define __A1_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 6
+#define CLKID_FCLK_DIV3 7
+#define CLKID_FCLK_DIV5 8
+#define CLKID_FCLK_DIV7 9
+#define CLKID_HIFI_PLL 10
+
+#endif /* __A1_PLL_CLKC_H */
--
2.24.0
next prev parent reply other threads:[~2019-12-06 7:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 7:40 [PATCH v4 0/6] add Amlogic A1 clock controller driver Jian Hu
2019-12-06 7:40 ` Jian Hu [this message]
2019-12-12 9:57 ` [PATCH v4 1/6] dt-bindings: clock: meson: add A1 PLL clock controller bindings Jerome Brunet
2019-12-13 9:35 ` Jian Hu
2019-12-13 10:38 ` Maxime Ripard
2019-12-18 8:00 ` Jian Hu
2019-12-18 12:57 ` Maxime Ripard
2019-12-06 7:40 ` [PATCH v4 2/6] clk: meson: add support for A1 PLL clock ops Jian Hu
2019-12-12 10:16 ` Jerome Brunet
2019-12-17 8:41 ` Jian Hu
2019-12-17 9:29 ` Jerome Brunet
2019-12-18 8:37 ` Jian Hu
2019-12-20 7:03 ` Jian Hu
2019-12-06 7:40 ` [PATCH v4 3/6] clk: meson: eeclk: refactor eeclk common driver to support A1 Jian Hu
2019-12-12 10:19 ` Jerome Brunet
2019-12-17 9:36 ` Jian Hu
2019-12-06 7:40 ` [PATCH v4 4/6] clk: meson: a1: add support for Amlogic A1 PLL clock driver Jian Hu
2019-12-12 10:28 ` Jerome Brunet
2019-12-12 10:42 ` Jerome Brunet
2019-12-18 6:01 ` Jian Hu
2019-12-06 7:40 ` [PATCH v4 5/6] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Jian Hu
2019-12-12 9:59 ` Jerome Brunet
2019-12-18 7:00 ` Jian Hu
2019-12-06 7:40 ` [PATCH v4 6/6] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Jian Hu
2019-12-12 11:01 ` Jerome Brunet
2019-12-18 7:20 ` Jian Hu
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