From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D2E9C2D0C0 for ; Mon, 16 Dec 2019 10:48:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29C4C206D3 for ; Mon, 16 Dec 2019 10:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727576AbfLPKsY (ORCPT ); Mon, 16 Dec 2019 05:48:24 -0500 Received: from foss.arm.com ([217.140.110.172]:49598 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727099AbfLPKsX (ORCPT ); Mon, 16 Dec 2019 05:48:23 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1DBE1FB; Mon, 16 Dec 2019 02:48:22 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 57EF93F6CF; Mon, 16 Dec 2019 02:48:22 -0800 (PST) Date: Mon, 16 Dec 2019 10:48:20 +0000 From: Andrew Murray To: Anvesh Salveru Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, kishon@ti.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, pankaj.dubey@samsung.com, mark.rutland@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v6 2/2] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Message-ID: <20191216104820.GQ24359@e119886-lin.cambridge.arm.com> References: <1576242800-23969-1-git-send-email-anvesh.s@samsung.com> <1576242800-23969-3-git-send-email-anvesh.s@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1576242800-23969-3-git-send-email-anvesh.s@samsung.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 13, 2019 at 06:43:20PM +0530, Anvesh Salveru wrote: > Many platforms use DesignWare controller but the PHY can be different in > different platforms. If the PHY is compliant is to ZRX-DC specification > it helps in low power consumption during power states. > > If current data rate is 8.0 GT/s or higher and PHY is not compliant to > ZRX-DC specification, then after every 100ms link should transition to > recovery state during the low power states. > > DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in > GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. > > Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable > to specify this property to the controller. > > Signed-off-by: Anvesh Salveru > Signed-off-by: Pankaj Dubey > --- > Changes w.r.t v5: > - None > > drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++ > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 820488d..36a01b7 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci) > PCIE_PL_CHK_REG_CHK_REG_START; > dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); > } > + > + if (pci->phy_zrxdc_compliant) { This series doesn't update any DWC drivers to actually test and set the phy_zrxdc_compliant flag. There isn't good justification for merging this unless it has a user. Thanks, Andrew Murray > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); > + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > + } > } > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 5accdd6..36f7579 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -60,6 +60,9 @@ > #define PCIE_MSI_INTR0_MASK 0x82C > #define PCIE_MSI_INTR0_STATUS 0x830 > > +#define PCIE_PORT_GEN3_RELATED 0x890 > +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) > + > #define PCIE_ATU_VIEWPORT 0x900 > #define PCIE_ATU_REGION_INBOUND BIT(31) > #define PCIE_ATU_REGION_OUTBOUND 0 > @@ -249,6 +252,7 @@ struct dw_pcie { > void __iomem *atu_base; > u32 num_viewport; > u8 iatu_unroll_enabled; > + bool phy_zrxdc_compliant; > struct pcie_port pp; > struct dw_pcie_ep ep; > const struct dw_pcie_ops *ops; > -- > 2.7.4 >