From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F1C5C43603 for ; Mon, 16 Dec 2019 18:38:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BADA20684 for ; Mon, 16 Dec 2019 18:38:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576521527; bh=J3ODutVrZsPdiTMVNV1fo4/+fpdWuhjHzTH1YZDgb/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=1AjEGF+uNhRIevR9M4HkYUY56AnzF8wJyKnIOaL10BPMW6pCZO2ir5bP+9iwsMcrM xpm7YnA853neAJyQYamKNUx/X0THW9QvsEudCxOzFUX2cl4O1EnqtpHZLmckpkNSWv BFgWIqwcjqZIYAj1XuV98QiB9wuYJoMU3wjgDIiM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729780AbfLPSip (ORCPT ); Mon, 16 Dec 2019 13:38:45 -0500 Received: from mail.kernel.org ([198.145.29.99]:41768 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729658AbfLPSE2 (ORCPT ); Mon, 16 Dec 2019 13:04:28 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 88F282072D; Mon, 16 Dec 2019 18:04:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576519468; bh=J3ODutVrZsPdiTMVNV1fo4/+fpdWuhjHzTH1YZDgb/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pIMUIdMvwiiDMKjb8oQrTF5qfn4vSjEpk7LQ+AqQvuYh1XtTWBupdIb9fG4au8faH 5eqRNg5GbMCtp7w0mUWpuLS/Fouqqc6eFpXuLjv6qISUqhzm7/oG5WCIMsIuSbz1Bu j14K3pvqIhuAub3S4CcBEdoxn1bzYU9MI+9TVBKU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Russell King , Gregory CLEMENT , Linus Walleij Subject: [PATCH 4.19 077/140] pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type() Date: Mon, 16 Dec 2019 18:49:05 +0100 Message-Id: <20191216174808.282066907@linuxfoundation.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191216174747.111154704@linuxfoundation.org> References: <20191216174747.111154704@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gregory CLEMENT commit 04fb02757ae5188031eb71b2f6f189edb1caf5dc upstream. As explained in the following commit a9a1a4833613 ("pinctrl: armada-37xx: Fix gpio interrupt setup") the armada_37xx_irq_set_type() function can be called before the initialization of the mask field. That means that we can't use this field in this function and need to workaround it using hwirq. Fixes: 30ac0d3b0702 ("pinctrl: armada-37xx: Add edge both type gpio irq support") Cc: stable@vger.kernel.org Reported-by: Russell King Signed-off-by: Gregory CLEMENT Link: https://lore.kernel.org/r/20191115155752.2562-1-gregory.clement@bootlin.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -592,10 +592,10 @@ static int armada_37xx_irq_set_type(stru regmap_read(info->regmap, in_reg, &in_val); /* Set initial polarity based on current input level. */ - if (in_val & d->mask) - val |= d->mask; /* falling */ + if (in_val & BIT(d->hwirq % GPIO_PER_REG)) + val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ else - val &= ~d->mask; /* rising */ + val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ break; } default: