From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Andrew Murray <andrew.murray@arm.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org
Subject: Re: [PATCH 10/13] dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
Date: Wed, 18 Dec 2019 18:14:08 -0600 [thread overview]
Message-ID: <20191219001408.GA20303@bogus> (raw)
In-Reply-To: <20191209092147.22901-11-kishon@ti.com>
On Mon, Dec 09, 2019 at 02:51:44PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe EP mode dt-bindings for TI's J721E SoC.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../bindings/pci/ti,j721e-pci-ep.yaml | 113 ++++++++++++++++++
> 1 file changed, 113 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> new file mode 100644
> index 000000000000..4e2af4733998
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> @@ -0,0 +1,113 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: TI J721E PCI EP (PCIe Wrapper)
> +
> +maintainers:
> + - Kishon Vijay Abraham I <kishon@ti.com>
> +
> +properties:
> + compatible:
> + enum:
> + - ti,j721e-pcie-ep
Indentation.
> +
> + reg:
> + maxItems: 4
> +
> + reg-names:
> + items:
> + - const: intd_cfg
> + - const: user_cfg
> + - const: reg
> + - const: mem
> +
> + ti,syscon-pcie-ctrl:
> + description: Phandle to the SYSCON entry required for configuring PCIe mode
> + and link speed.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/phandle
> +
> + max-link-speed:
> + minimum: 1
> + maximum: 3
> +
> + num-lanes:
> + minimum: 1
> + maximum: 2
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> + description: clock-specifier to represent input to the PCIe
> +
> + clock-names:
> + items:
> + - const: fck
> +
> + cdns,max-outbound-regions:
> + description: As defined in
> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/int32
uint32
> + - enum: [16]
> +
> + max-functions:
> + minimum: 1
> + maximum: 6
Needs a type ref. Or a common definition.
> +
> + dma-coherent:
> + description: Indicates that the PCIe IP block can ensure the coherency
> +
> + phys:
How many? Need to convert cdns,cdns-pcie-host.txt...
> + description: As defined in
> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> +
> + phy-names:
> + description: As defined in
> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
For all the properties shared with host mode, it might make sense to
define a common schema with all those properties and then include it in
the host and endpoint schemas.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - ti,syscon-pcie-ctrl
> + - max-link-speed
> + - num-lanes
> + - power-domains
> + - clocks
> + - clock-names
> + - cdns,max-outbound-regions
> + - dma-coherent
> + - max-functions
> + - phys
> + - phy-names
> +
> +examples:
> + - |
> + #include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> + pcie0_ep: pcie-ep@d000000 {
> + compatible = "ti,j721e-pcie-ep";
> + reg = <0x00 0x02900000 0x00 0x1000>,
> + <0x00 0x02907000 0x00 0x400>,
> + <0x00 0x0d000000 0x00 0x00800000>,
> + <0x00 0x10000000 0x00 0x08000000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "mem";
> + ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
> + max-link-speed = <3>;
> + num-lanes = <2>;
> + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 239 1>;
> + clock-names = "fck";
> + cdns,max-outbound-regions = <16>;
> + max-functions = /bits/ 8 <6>;
> + dma-coherent;
> + phys = <&serdes0_pcie_link>;
> + phy-names = "pcie_phy";
> + };
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-12-19 0:14 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45 ` Andrew Murray
2019-12-19 8:31 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07 ` Andrew Murray
2019-12-19 11:41 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58 ` Andrew Murray
2019-12-19 12:01 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15 ` Bjorn Helgaas
2019-12-16 14:49 ` Andrew Murray
2019-12-19 11:56 ` Kishon Vijay Abraham I
2019-12-19 12:03 ` Arnd Bergmann
2019-12-19 13:19 ` Kishon Vijay Abraham I
2019-12-19 20:16 ` Arnd Bergmann
2019-12-17 23:36 ` Bjorn Helgaas
2019-12-19 12:49 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32 ` Andrew Murray
2019-12-19 12:02 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40 ` Andrew Murray
2019-12-19 12:03 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42 ` Andrew Murray
2019-12-19 12:12 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19 0:08 ` Rob Herring
2019-12-19 13:13 ` Kishon Vijay Abraham I
2019-12-24 8:06 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19 0:14 ` Rob Herring [this message]
2019-12-19 13:14 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23 ` Andrew Murray
2019-12-19 22:47 ` Bjorn Helgaas
2019-12-09 9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
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