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[2003:f1:373a:1900:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id q3sm32911665wrn.33.2019.12.26.12.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2019 12:37:13 -0800 (PST) From: Martin Blumenstingl To: andrew@lunn.ch, f.fainelli@gmail.com, linux-amlogic@lists.infradead.org, jianxin.pan@amlogic.com Cc: davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [RFC v1 2/2] net: stmmac: dwmac-meson8b: add support for the RX delay configuration Date: Thu, 26 Dec 2019 21:36:55 +0100 Message-Id: <20191226203655.4046170-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191226203655.4046170-1-martin.blumenstingl@googlemail.com> References: <20191226203655.4046170-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DO NOT MERGE THIS! Test results: - Akaso M8S (not upstream yet) Meson8m2 with RMII PHY: no change - Odroid-C1 Meson8b with RTL8211F RGMII PHY: phy-mode = "rgmii" still works phy-mode = "rgmii-id" works now - Khadas VIM2 GXM with RTL8211F RGMII PHY: phy-mode = "rgmii" is now broken! phy-mode = "rgmii-id" works The public A311D datasheet [0] mentions these bits in the PRG_ETH0 (also call PRG_ETH0_REG) register: - bit[13]: RMII & RGMII mode, Enable data delay adjustment and calibration logic. - bit[14]: Set RXDV and RXD setup time, data is aligned with index 0. When set to 1, auto delay and skew. - bit[19:15]: Set bit14 to 0. RMII & RGMII mode. Capture input data at clock index equal to adj_delay. - bit[24:20]: RMII & RGMII mode. 5 Bits correspondent to {RXDV, RXD[3:0]}, set to 1 will delay the data capture by 1 cycle. (do all of these bits have the same meaning for all supported SoCs: Meson8b, Meson8m2, GXBB, GXL, GXM, AXG, G12A, G12B, SM1?) The public "Amlogic Ethernet controller user guide" recommends the following settings. RMII: adj_enable = 1, adj_setup = 0, adj_delay = 18, adj_skew = 0x0 RGMII: adj_enable = 1, adj_setup = 1, adj_delay = 4, adj_skew = 0xc (shouldn't adj_delay be 0 for the RGMII mode based on the register description above?) Do we need to expose adj_delay and adj_skew to devicetree? How do I know which value to set for each board? [0] https://dl.khadas.com/Hardware/VIM3/Datasheet/A311D_Datasheet_01_Wesion.pdf [1] http://openlinux.amlogic.com/@api/deki/files/75/=Amlogic_Ethenet_controller_user_Guide.pdf Signed-off-by: Martin Blumenstingl --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 59 ++++++++++--------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 1483761ab1e6..af25eb1aea41 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -33,6 +33,10 @@ #define PRG_ETH0_CLK_M250_SEL_SHIFT 4 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) +/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one + * cycle of the 125MHz RGMII TX clock): + * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 + */ #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) /* divider for the result of m250_sel */ @@ -44,6 +48,11 @@ #define PRG_ETH0_INVERTED_RMII_CLK BIT(11) #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) +#define PRG_ETH0_ADJ_ENABLE BIT(13) +#define PRG_ETH0_ADJ_SETUP BIT(14) +#define PRG_ETH0_ADJ_DELAY GENMASK(19, 15) +#define PRG_ETH0_ADJ_SKEW GENMASK(24, 20) + #define MUX_CLK_NUM_PARENTS 2 struct meson8b_dwmac; @@ -241,29 +250,38 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { + u8 tx_dly_val = dwmac->tx_delay_ns >> 1; + u32 delay_config; int ret; - u8 tx_dly_val = 0; switch (dwmac->phy_mode) { case PHY_INTERFACE_MODE_RGMII: + delay_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK, tx_dly_val); + delay_config |= PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP; + break; case PHY_INTERFACE_MODE_RGMII_RXID: - /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where - * 8ns are exactly one cycle of the 125MHz RGMII TX clock): - * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 - */ - tx_dly_val = dwmac->tx_delay_ns >> 1; - /* fall through */ - - case PHY_INTERFACE_MODE_RGMII_ID: + delay_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK, tx_dly_val); + break; case PHY_INTERFACE_MODE_RGMII_TXID: + delay_config = PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RMII: + default: + delay_config = 0; + break; + }; + + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK | + PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP | + PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW, + delay_config); + + if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) { /* only relevant for RMII mode -> disable in RGMII mode */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, 0); - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, - FIELD_PREP(PRG_ETH0_TXDLY_MASK, - tx_dly_val)); - /* Configure the 125MHz RGMII TX clock, the IP block changes * the output automatically (= without us having to configure * a register) based on the line-speed (125MHz for Gbit speeds, @@ -286,24 +304,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) devm_add_action_or_reset(dwmac->dev, (void(*)(void *))clk_disable_unprepare, dwmac->rgmii_tx_clk); - break; - - case PHY_INTERFACE_MODE_RMII: + } else { /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, PRG_ETH0_INVERTED_RMII_CLK); - - /* TX clock delay cannot be configured in RMII mode */ - meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, - 0); - - break; - - default: - dev_err(dwmac->dev, "unsupported phy-mode %s\n", - phy_modes(dwmac->phy_mode)); - return -EINVAL; } /* enable TX_CLK and PHY_REF_CLK generator */ -- 2.24.1