[PATCH V2 0/5] Add support to defer core initialization

[PATCH V2 0/5] Add support to defer core initialization

[Vidya Sagar]

EPC/DesignWare core endpoint subsystems assume that the core registers are
available always for SW to initialize. But, that may not be the case always.
For example, Tegra194 hardware has the core running on a clock that is derived
from reference clock that is coming into the endpoint system from host.
Hence core is made available asynchronously based on when host system is going
for enumeration of devices. To accommodate this kind of hardwares, support is
required to defer the core initialization until the respective platform driver
informs the EPC/DWC endpoint sub-systems that the core is indeed available for
initiaization. This patch series is attempting to add precisely that.
This series is based on Kishon's patch that adds notification mechanism
support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/

Vidya Sagar (5):
  PCI: endpoint: Add core init notifying feature
  PCI: dwc: Refactor core initialization code for EP mode
  PCI: endpoint: Add notification for core init completion
  PCI: dwc: Add API to notify core initialization completion
  PCI: pci-epf-test: Add support to defer core initialization

 .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
 drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
 drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
 drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
 include/linux/pci-epc.h                       |   2 +
 include/linux/pci-epf.h                       |   5 +
 6 files changed, 164 insertions(+), 70 deletions(-)

-- 
2.17.1

[PATCH V2 1/5] PCI: endpoint: Add core init notifying feature

[Vidya Sagar]

Add a new feature core_init_notifier for cores that can notify about
their availability for initialization (Ex:- Tegra194).

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* This is a new patch in this series

 include/linux/pci-epc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 36644ccd32ac..ec8d4d896564 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -115,6 +115,7 @@ struct pci_epc {
  */
 struct pci_epc_features {
 	unsigned int	linkup_notifier : 1;
+	unsigned int	core_init_notifier : 1;
 	unsigned int	msi_capable : 1;
 	unsigned int	msix_capable : 1;
 	u8	reserved_bar;
-- 
2.17.1

[PATCH V2 2/5] PCI: dwc: Refactor core initialization code for EP mode

[Vidya Sagar]

Splits core initialization code for EP mode into two, one that doesn't
touch core registers and the other that touches core registers. The latter
would be called/skipped based on the EPC feature 'core_init_notifier'.
In case of platforms where this is skipped (Ex:- Tegra194), it would be
called indirectly through hooks from the function driver.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* Changed EPC feature name from 'skip_core_init' to 'core_init_notifier'
* Made the pci-epc.h header file change as a separate patch as per the review
  comment from Kishon

 .../pci/controller/dwc/pcie-designware-ep.c   | 72 +++++++++++--------
 drivers/pci/controller/dwc/pcie-designware.h  |  6 ++
 2 files changed, 50 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 3dd2e2697294..c0ff34e5a1e3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
 	return 0;
 }
 
-int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 {
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	unsigned int offset;
+	unsigned int nbars;
+	u8 hdr_type;
+	u32 reg;
 	int i;
+
+	hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+	if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+		dev_err(pci->dev,
+			"PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+			hdr_type);
+		return -EIO;
+	}
+
+	ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+
+	ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+
+	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+	if (offset) {
+		reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
+		nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
+			PCI_REBAR_CTRL_NBAR_SHIFT;
+
+		dw_pcie_dbi_ro_wr_en(pci);
+		for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
+			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
+		dw_pcie_dbi_ro_wr_dis(pci);
+	}
+
+	dw_pcie_setup(pci);
+
+	return 0;
+}
+
+int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
 	int ret;
-	u32 reg;
 	void *addr;
-	u8 hdr_type;
-	unsigned int nbars;
-	unsigned int offset;
 	struct pci_epc *epc;
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
+	const struct pci_epc_features *epc_features;
 
 	if (!pci->dbi_base || !pci->dbi_base2) {
 		dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
@@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	if (ep->ops->ep_init)
 		ep->ops->ep_init(ep);
 
-	hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
-	if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
-		dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
-			hdr_type);
-		return -EIO;
-	}
-
 	ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
 	if (ret < 0)
 		epc->max_functions = 1;
@@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
 		return -ENOMEM;
 	}
-	ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
 
-	ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
-
-	offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
-	if (offset) {
-		reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
-		nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
-			PCI_REBAR_CTRL_NBAR_SHIFT;
-
-		dw_pcie_dbi_ro_wr_en(pci);
-		for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
-			dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
-		dw_pcie_dbi_ro_wr_dis(pci);
+	if (ep->ops->get_features) {
+		epc_features = ep->ops->get_features(ep);
+		if (epc_features->core_init_notifier)
+			return 0;
 	}
 
-	dw_pcie_setup(pci);
-
-	return 0;
+	return dw_pcie_ep_init_complete(ep);
 }
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 5accdd6bc388..340783e9032e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -399,6 +399,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
 #ifdef CONFIG_PCIE_DW_EP
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -416,6 +417,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	return 0;
 }
 
+static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
+{
+	return 0;
+}
+
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
-- 
2.17.1

[PATCH V2 3/5] PCI: endpoint: Add notification for core init completion

[Vidya Sagar]

Add support to send notifications to EPF from EPC once the core
registers initialization is complete.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* None

 drivers/pci/endpoint/pci-epc-core.c | 19 ++++++++++++++++++-
 include/linux/pci-epc.h             |  1 +
 include/linux/pci-epf.h             |  5 +++++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 2f6436599fcb..fcc3f7fb19c0 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -542,10 +542,27 @@ void pci_epc_linkup(struct pci_epc *epc)
 	if (!epc || IS_ERR(epc))
 		return;
 
-	atomic_notifier_call_chain(&epc->notifier, 0, NULL);
+	atomic_notifier_call_chain(&epc->notifier, LINK_UP, NULL);
 }
 EXPORT_SYMBOL_GPL(pci_epc_linkup);
 
+/**
+ * pci_epc_init_notify() - Notify the EPF device that EPC device's core
+ *			   initialization is completed.
+ * @epc: the EPC device whose core initialization is completeds
+ *
+ * Invoke to Notify the EPF device that the EPC device's initialization
+ * is completed.
+ */
+void pci_epc_init_notify(struct pci_epc *epc)
+{
+	if (!epc || IS_ERR(epc))
+		return;
+
+	atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL);
+}
+EXPORT_SYMBOL_GPL(pci_epc_init_notify);
+
 /**
  * pci_epc_destroy() - destroy the EPC device
  * @epc: the EPC device that has to be destroyed
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index ec8d4d896564..31cdae7e2cdd 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -160,6 +160,7 @@ void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
 void pci_epc_destroy(struct pci_epc *epc);
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
 void pci_epc_linkup(struct pci_epc *epc);
+void pci_epc_init_notify(struct pci_epc *epc);
 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
 int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
 			 struct pci_epf_header *hdr);
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 4993f7f6439b..3cb65ac1648c 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -15,6 +15,11 @@
 
 struct pci_epf;
 
+enum pci_notify_event {
+	CORE_INIT,
+	LINK_UP,
+};
+
 enum pci_barno {
 	BAR_0,
 	BAR_1,
-- 
2.17.1

[PATCH V2 4/5] PCI: dwc: Add API to notify core initialization completion

[Vidya Sagar]

Add a new API dw_pcie_ep_init_notify() to let platform drivers
call it when the core is available for initialization.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* None

 drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++++
 drivers/pci/controller/dwc/pcie-designware.h    | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index c0ff34e5a1e3..9da2689e77df 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -19,6 +19,13 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
 	pci_epc_linkup(epc);
 }
 
+void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
+{
+	struct pci_epc *epc = ep->epc;
+
+	pci_epc_init_notify(epc);
+}
+
 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
 				   int flags)
 {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 340783e9032e..f62c5bae6b2d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -400,6 +400,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
+void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -422,6 +423,10 @@ static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 	return 0;
 }
 
+static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
+{
+}
+
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
-- 
2.17.1

[PATCH V2 5/5] PCI: pci-epf-test: Add support to defer core initialization

[Vidya Sagar]

Add support to defer core initialization and to receive a notifier
when core is ready to accommodate platforms where core is not for
initialization untile reference clock from host is available.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* Addressed review comments from Kishon

 drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
 1 file changed, 77 insertions(+), 41 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index bddff15052cc..be04c6220265 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -360,18 +360,6 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
 			   msecs_to_jiffies(1));
 }
 
-static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
-				 void *data)
-{
-	struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
-	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
-
-	queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
-			   msecs_to_jiffies(1));
-
-	return NOTIFY_OK;
-}
-
 static void pci_epf_test_unbind(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
@@ -428,6 +416,78 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 	return 0;
 }
 
+static int pci_epf_test_core_init(struct pci_epf *epf)
+{
+	struct pci_epf_header *header = epf->header;
+	const struct pci_epc_features *epc_features;
+	struct pci_epc *epc = epf->epc;
+	struct device *dev = &epf->dev;
+	bool msix_capable = false;
+	bool msi_capable = true;
+	int ret;
+
+	epc_features = pci_epc_get_features(epc, epf->func_no);
+	if (epc_features) {
+		msix_capable = epc_features->msix_capable;
+		msi_capable = epc_features->msi_capable;
+	}
+
+	ret = pci_epc_write_header(epc, epf->func_no, header);
+	if (ret) {
+		dev_err(dev, "Configuration header write failed\n");
+		return ret;
+	}
+
+	ret = pci_epf_test_set_bar(epf);
+	if (ret)
+		return ret;
+
+	if (msi_capable) {
+		ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
+		if (ret) {
+			dev_err(dev, "MSI configuration failed\n");
+			return ret;
+		}
+	}
+
+	if (msix_capable) {
+		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
+		if (ret) {
+			dev_err(dev, "MSI-X configuration failed\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
+				 void *data)
+{
+	struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
+	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+	int ret;
+
+	switch (val) {
+	case CORE_INIT:
+		ret = pci_epf_test_core_init(epf);
+		if (ret)
+			return NOTIFY_BAD;
+		break;
+
+	case LINK_UP:
+		queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
+				   msecs_to_jiffies(1));
+		break;
+
+	default:
+		dev_err(&epf->dev, "Invalid EPF test notifier event\n");
+		return NOTIFY_BAD;
+	}
+
+	return NOTIFY_OK;
+}
+
 static int pci_epf_test_alloc_space(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
@@ -496,14 +556,11 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 {
 	int ret;
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
-	struct pci_epf_header *header = epf->header;
 	const struct pci_epc_features *epc_features;
 	enum pci_barno test_reg_bar = BAR_0;
 	struct pci_epc *epc = epf->epc;
-	struct device *dev = &epf->dev;
 	bool linkup_notifier = false;
-	bool msix_capable = false;
-	bool msi_capable = true;
+	bool core_init_notifier = false;
 
 	if (WARN_ON_ONCE(!epc))
 		return -EINVAL;
@@ -511,8 +568,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	epc_features = pci_epc_get_features(epc, epf->func_no);
 	if (epc_features) {
 		linkup_notifier = epc_features->linkup_notifier;
-		msix_capable = epc_features->msix_capable;
-		msi_capable = epc_features->msi_capable;
+		core_init_notifier = epc_features->core_init_notifier;
 		test_reg_bar = pci_epc_get_first_free_bar(epc_features);
 		pci_epf_configure_bar(epf, epc_features);
 	}
@@ -520,34 +576,14 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	epf_test->test_reg_bar = test_reg_bar;
 	epf_test->epc_features = epc_features;
 
-	ret = pci_epc_write_header(epc, epf->func_no, header);
-	if (ret) {
-		dev_err(dev, "Configuration header write failed\n");
-		return ret;
-	}
-
 	ret = pci_epf_test_alloc_space(epf);
 	if (ret)
 		return ret;
 
-	ret = pci_epf_test_set_bar(epf);
-	if (ret)
-		return ret;
-
-	if (msi_capable) {
-		ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
-		if (ret) {
-			dev_err(dev, "MSI configuration failed\n");
-			return ret;
-		}
-	}
-
-	if (msix_capable) {
-		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
-		if (ret) {
-			dev_err(dev, "MSI-X configuration failed\n");
+	if (!core_init_notifier) {
+		ret = pci_epf_test_core_init(epf);
+		if (ret)
 			return ret;
-		}
 	}
 
 	if (linkup_notifier) {
-- 
2.17.1

Re: [PATCH V2 0/5] Add support to defer core initialization

[Vidya Sagar]

Hi Kishon,
Could you please review this series?

Also, this series depends on the following change of yours
http://patchwork.ozlabs.org/patch/1109884/
Whats the plan to get this merged?

Thanks,
Vidya Sagar

On 1/3/20 3:37 PM, Vidya Sagar wrote:
> EPC/DesignWare core endpoint subsystems assume that the core registers are
> available always for SW to initialize. But, that may not be the case always.
> For example, Tegra194 hardware has the core running on a clock that is derived
> from reference clock that is coming into the endpoint system from host.
> Hence core is made available asynchronously based on when host system is going
> for enumeration of devices. To accommodate this kind of hardwares, support is
> required to defer the core initialization until the respective platform driver
> informs the EPC/DWC endpoint sub-systems that the core is indeed available for
> initiaization. This patch series is attempting to add precisely that.
> This series is based on Kishon's patch that adds notification mechanism
> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
> 
> Vidya Sagar (5):
>    PCI: endpoint: Add core init notifying feature
>    PCI: dwc: Refactor core initialization code for EP mode
>    PCI: endpoint: Add notification for core init completion
>    PCI: dwc: Add API to notify core initialization completion
>    PCI: pci-epf-test: Add support to defer core initialization
> 
>   .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>   drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>   drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>   drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>   include/linux/pci-epc.h                       |   2 +
>   include/linux/pci-epf.h                       |   5 +
>   6 files changed, 164 insertions(+), 70 deletions(-)
> 

Re: [PATCH V2 0/5] Add support to defer core initialization

[Vidya Sagar]

Hi Kishon,
Apologies for pinging again. Could you please review this series?

Thanks,
Vidya Sagar

On 1/11/2020 5:18 PM, Vidya Sagar wrote:
> Hi Kishon,
> Could you please review this series?
> 
> Also, this series depends on the following change of yours
> http://patchwork.ozlabs.org/patch/1109884/
> Whats the plan to get this merged?
> 
> Thanks,
> Vidya Sagar
> 
> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>> EPC/DesignWare core endpoint subsystems assume that the core registers 
>> are
>> available always for SW to initialize. But, that may not be the case 
>> always.
>> For example, Tegra194 hardware has the core running on a clock that is 
>> derived
>> from reference clock that is coming into the endpoint system from host.
>> Hence core is made available asynchronously based on when host system 
>> is going
>> for enumeration of devices. To accommodate this kind of hardwares, 
>> support is
>> required to defer the core initialization until the respective 
>> platform driver
>> informs the EPC/DWC endpoint sub-systems that the core is indeed 
>> available for
>> initiaization. This patch series is attempting to add precisely that.
>> This series is based on Kishon's patch that adds notification mechanism
>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>
>> Vidya Sagar (5):
>>    PCI: endpoint: Add core init notifying feature
>>    PCI: dwc: Refactor core initialization code for EP mode
>>    PCI: endpoint: Add notification for core init completion
>>    PCI: dwc: Add API to notify core initialization completion
>>    PCI: pci-epf-test: Add support to defer core initialization
>>
>>   .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>   drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>   drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>   drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>   include/linux/pci-epc.h                       |   2 +
>>   include/linux/pci-epf.h                       |   5 +
>>   6 files changed, 164 insertions(+), 70 deletions(-)
>>

Re: [PATCH V2 0/5] Add support to defer core initialization

[Kishon Vijay Abraham I]

Hi Vidya Sagar,

On 23/01/20 2:54 pm, Vidya Sagar wrote:
> Hi Kishon,
> Apologies for pinging again. Could you please review this series?
> 
> Thanks,
> Vidya Sagar
> 
> On 1/11/2020 5:18 PM, Vidya Sagar wrote:
>> Hi Kishon,
>> Could you please review this series?
>>
>> Also, this series depends on the following change of yours
>> http://patchwork.ozlabs.org/patch/1109884/
>> Whats the plan to get this merged?

I've posted the endpoint improvements as a separate series
http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com

I'd prefer this series gets tested by others. I'm also planning to test
this series. Sorry for the delay. I'll test review and test this series
early next week.

Thanks
Kishon

>>
>> Thanks,
>> Vidya Sagar
>>
>> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>>> EPC/DesignWare core endpoint subsystems assume that the core
>>> registers are
>>> available always for SW to initialize. But, that may not be the case
>>> always.
>>> For example, Tegra194 hardware has the core running on a clock that
>>> is derived
>>> from reference clock that is coming into the endpoint system from host.
>>> Hence core is made available asynchronously based on when host system
>>> is going
>>> for enumeration of devices. To accommodate this kind of hardwares,
>>> support is
>>> required to defer the core initialization until the respective
>>> platform driver
>>> informs the EPC/DWC endpoint sub-systems that the core is indeed
>>> available for
>>> initiaization. This patch series is attempting to add precisely that.
>>> This series is based on Kishon's patch that adds notification mechanism
>>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>>
>>> Vidya Sagar (5):
>>>    PCI: endpoint: Add core init notifying feature
>>>    PCI: dwc: Refactor core initialization code for EP mode
>>>    PCI: endpoint: Add notification for core init completion
>>>    PCI: dwc: Add API to notify core initialization completion
>>>    PCI: pci-epf-test: Add support to defer core initialization
>>>
>>>   .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>>   drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>>   drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>>   drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>>   include/linux/pci-epc.h                       |   2 +
>>>   include/linux/pci-epf.h                       |   5 +
>>>   6 files changed, 164 insertions(+), 70 deletions(-)
>>>

Re: [PATCH V2 0/5] Add support to defer core initialization

[Vidya Sagar]

On 1/23/2020 3:25 PM, Kishon Vijay Abraham I wrote:
> External email: Use caution opening links or attachments
> 
> 
> Hi Vidya Sagar,
> 
> On 23/01/20 2:54 pm, Vidya Sagar wrote:
>> Hi Kishon,
>> Apologies for pinging again. Could you please review this series?
>>
>> Thanks,
>> Vidya Sagar
>>
>> On 1/11/2020 5:18 PM, Vidya Sagar wrote:
>>> Hi Kishon,
>>> Could you please review this series?
>>>
>>> Also, this series depends on the following change of yours
>>> http://patchwork.ozlabs.org/patch/1109884/
>>> Whats the plan to get this merged?
> 
> I've posted the endpoint improvements as a separate series
> http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com
> 
> I'd prefer this series gets tested by others. I'm also planning to test
> this series. Sorry for the delay. I'll test review and test this series
> early next week.
Hi Kishon,
Just wanted to know if you got time to test review my patches.

Thanks,
Vidya Sagar

> 
> Thanks
> Kishon
> 
>>>
>>> Thanks,
>>> Vidya Sagar
>>>
>>> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>>>> EPC/DesignWare core endpoint subsystems assume that the core
>>>> registers are
>>>> available always for SW to initialize. But, that may not be the case
>>>> always.
>>>> For example, Tegra194 hardware has the core running on a clock that
>>>> is derived
>>>> from reference clock that is coming into the endpoint system from host.
>>>> Hence core is made available asynchronously based on when host system
>>>> is going
>>>> for enumeration of devices. To accommodate this kind of hardwares,
>>>> support is
>>>> required to defer the core initialization until the respective
>>>> platform driver
>>>> informs the EPC/DWC endpoint sub-systems that the core is indeed
>>>> available for
>>>> initiaization. This patch series is attempting to add precisely that.
>>>> This series is based on Kishon's patch that adds notification mechanism
>>>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>>>
>>>> Vidya Sagar (5):
>>>>     PCI: endpoint: Add core init notifying feature
>>>>     PCI: dwc: Refactor core initialization code for EP mode
>>>>     PCI: endpoint: Add notification for core init completion
>>>>     PCI: dwc: Add API to notify core initialization completion
>>>>     PCI: pci-epf-test: Add support to defer core initialization
>>>>
>>>>    .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>>>    drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>>>    drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>>>    drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>>>    include/linux/pci-epc.h                       |   2 +
>>>>    include/linux/pci-epf.h                       |   5 +
>>>>    6 files changed, 164 insertions(+), 70 deletions(-)
>>>>

Re: [PATCH V2 0/5] Add support to defer core initialization

[Kishon Vijay Abraham I]

+Tom, Milind

Hi,

On 23/01/20 3:25 PM, Kishon Vijay Abraham I wrote:
> Hi Vidya Sagar,
> 
> On 23/01/20 2:54 pm, Vidya Sagar wrote:
>> Hi Kishon,
>> Apologies for pinging again. Could you please review this series?
>>
>> Thanks,
>> Vidya Sagar
>>
>> On 1/11/2020 5:18 PM, Vidya Sagar wrote:
>>> Hi Kishon,
>>> Could you please review this series?
>>>
>>> Also, this series depends on the following change of yours
>>> http://patchwork.ozlabs.org/patch/1109884/
>>> Whats the plan to get this merged?
> 
> I've posted the endpoint improvements as a separate series
> http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com
> 
> I'd prefer this series gets tested by others. I'm also planning to test
> this series. Sorry for the delay. I'll test review and test this series
> early next week.

I tested this series with DRA7 configured in EP mode. So for the series
itself

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Tom, Can you test this series in Cadence platform?

Lorenzo, Andrew,

How do you want to go about merging this series? This series depends on
[1] which in turn is dependent on two other series. If required, I can
rebase [1] on mainline kernel and remove it's dependencies with the
other series. That way this series and [1] could be merged. And the
other series could be worked later. Kindly let me know.

Thanks
Kishon

[1] ->
https://lore.kernel.org/linux-pci/20191231100331.6316-1-kishon@ti.com/
> 
> Thanks
> Kishon
> 
>>>
>>> Thanks,
>>> Vidya Sagar
>>>
>>> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>>>> EPC/DesignWare core endpoint subsystems assume that the core
>>>> registers are
>>>> available always for SW to initialize. But, that may not be the case
>>>> always.
>>>> For example, Tegra194 hardware has the core running on a clock that
>>>> is derived
>>>> from reference clock that is coming into the endpoint system from host.
>>>> Hence core is made available asynchronously based on when host system
>>>> is going
>>>> for enumeration of devices. To accommodate this kind of hardwares,
>>>> support is
>>>> required to defer the core initialization until the respective
>>>> platform driver
>>>> informs the EPC/DWC endpoint sub-systems that the core is indeed
>>>> available for
>>>> initiaization. This patch series is attempting to add precisely that.
>>>> This series is based on Kishon's patch that adds notification mechanism
>>>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>>>
>>>> Vidya Sagar (5):
>>>>    PCI: endpoint: Add core init notifying feature
>>>>    PCI: dwc: Refactor core initialization code for EP mode
>>>>    PCI: endpoint: Add notification for core init completion
>>>>    PCI: dwc: Add API to notify core initialization completion
>>>>    PCI: pci-epf-test: Add support to defer core initialization
>>>>
>>>>   .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>>>   drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>>>   drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>>>   drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>>>   include/linux/pci-epc.h                       |   2 +
>>>>   include/linux/pci-epf.h                       |   5 +
>>>>   6 files changed, 164 insertions(+), 70 deletions(-)
>>>>

Re: [PATCH V2 0/5] Add support to defer core initialization

[Vidya Sagar]

Hi Lorenzo, Andrew,
Kishon did rebase [1] mentioned below and removed dependencies.
New patch series is available
@ http://patchwork.ozlabs.org/project/linux-pci/list/?series=158088

I rebased my patches on top of this and is available for review
@ http://patchwork.ozlabs.org/project/linux-pci/list/?series=158959

Please let us know the way forward towards merging these patches.

Thanks,
Vidya Sagar

On 2/5/2020 12:07 PM, Kishon Vijay Abraham I wrote:
> External email: Use caution opening links or attachments
> 
> 
> +Tom, Milind
> 
> Hi,
> 
> On 23/01/20 3:25 PM, Kishon Vijay Abraham I wrote:
>> Hi Vidya Sagar,
>>
>> On 23/01/20 2:54 pm, Vidya Sagar wrote:
>>> Hi Kishon,
>>> Apologies for pinging again. Could you please review this series?
>>>
>>> Thanks,
>>> Vidya Sagar
>>>
>>> On 1/11/2020 5:18 PM, Vidya Sagar wrote:
>>>> Hi Kishon,
>>>> Could you please review this series?
>>>>
>>>> Also, this series depends on the following change of yours
>>>> http://patchwork.ozlabs.org/patch/1109884/
>>>> Whats the plan to get this merged?
>>
>> I've posted the endpoint improvements as a separate series
>> http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com
>>
>> I'd prefer this series gets tested by others. I'm also planning to test
>> this series. Sorry for the delay. I'll test review and test this series
>> early next week.
> 
> I tested this series with DRA7 configured in EP mode. So for the series
> itself
> 
> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> 
> Tom, Can you test this series in Cadence platform?
> 
> Lorenzo, Andrew,
> 
> How do you want to go about merging this series? This series depends on
> [1] which in turn is dependent on two other series. If required, I can
> rebase [1] on mainline kernel and remove it's dependencies with the
> other series. That way this series and [1] could be merged. And the
> other series could be worked later. Kindly let me know.
> 
> Thanks
> Kishon
> 
> [1] ->
> https://lore.kernel.org/linux-pci/20191231100331.6316-1-kishon@ti.com/
>>
>> Thanks
>> Kishon
>>
>>>>
>>>> Thanks,
>>>> Vidya Sagar
>>>>
>>>> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>>>>> EPC/DesignWare core endpoint subsystems assume that the core
>>>>> registers are
>>>>> available always for SW to initialize. But, that may not be the case
>>>>> always.
>>>>> For example, Tegra194 hardware has the core running on a clock that
>>>>> is derived
>>>>> from reference clock that is coming into the endpoint system from host.
>>>>> Hence core is made available asynchronously based on when host system
>>>>> is going
>>>>> for enumeration of devices. To accommodate this kind of hardwares,
>>>>> support is
>>>>> required to defer the core initialization until the respective
>>>>> platform driver
>>>>> informs the EPC/DWC endpoint sub-systems that the core is indeed
>>>>> available for
>>>>> initiaization. This patch series is attempting to add precisely that.
>>>>> This series is based on Kishon's patch that adds notification mechanism
>>>>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>>>>
>>>>> Vidya Sagar (5):
>>>>>     PCI: endpoint: Add core init notifying feature
>>>>>     PCI: dwc: Refactor core initialization code for EP mode
>>>>>     PCI: endpoint: Add notification for core init completion
>>>>>     PCI: dwc: Add API to notify core initialization completion
>>>>>     PCI: pci-epf-test: Add support to defer core initialization
>>>>>
>>>>>    .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
>>>>>    drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
>>>>>    drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
>>>>>    drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
>>>>>    include/linux/pci-epc.h                       |   2 +
>>>>>    include/linux/pci-epf.h                       |   5 +
>>>>>    6 files changed, 164 insertions(+), 70 deletions(-)
>>>>>

Re: [PATCH V2 0/5] Add support to defer core initialization

[Lorenzo Pieralisi]

On Wed, Feb 19, 2020 at 07:06:47PM +0530, Vidya Sagar wrote:
> Hi Lorenzo, Andrew,
> Kishon did rebase [1] mentioned below and removed dependencies.
> New patch series is available
> @ http://patchwork.ozlabs.org/project/linux-pci/list/?series=158088
> 
> I rebased my patches on top of this and is available for review
> @ http://patchwork.ozlabs.org/project/linux-pci/list/?series=158959
> 
> Please let us know the way forward towards merging these patches.

Hi Vidya,

I shall have a look shortly, I have planned to start queueing patches
from next week.

Thanks,
Lorenzo

> Thanks,
> Vidya Sagar
> 
> On 2/5/2020 12:07 PM, Kishon Vijay Abraham I wrote:
> > External email: Use caution opening links or attachments
> > 
> > 
> > +Tom, Milind
> > 
> > Hi,
> > 
> > On 23/01/20 3:25 PM, Kishon Vijay Abraham I wrote:
> > > Hi Vidya Sagar,
> > > 
> > > On 23/01/20 2:54 pm, Vidya Sagar wrote:
> > > > Hi Kishon,
> > > > Apologies for pinging again. Could you please review this series?
> > > > 
> > > > Thanks,
> > > > Vidya Sagar
> > > > 
> > > > On 1/11/2020 5:18 PM, Vidya Sagar wrote:
> > > > > Hi Kishon,
> > > > > Could you please review this series?
> > > > > 
> > > > > Also, this series depends on the following change of yours
> > > > > http://patchwork.ozlabs.org/patch/1109884/
> > > > > Whats the plan to get this merged?
> > > 
> > > I've posted the endpoint improvements as a separate series
> > > http://lore.kernel.org/r/20191231100331.6316-1-kishon@ti.com
> > > 
> > > I'd prefer this series gets tested by others. I'm also planning to test
> > > this series. Sorry for the delay. I'll test review and test this series
> > > early next week.
> > 
> > I tested this series with DRA7 configured in EP mode. So for the series
> > itself
> > 
> > Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
> > 
> > Tom, Can you test this series in Cadence platform?
> > 
> > Lorenzo, Andrew,
> > 
> > How do you want to go about merging this series? This series depends on
> > [1] which in turn is dependent on two other series. If required, I can
> > rebase [1] on mainline kernel and remove it's dependencies with the
> > other series. That way this series and [1] could be merged. And the
> > other series could be worked later. Kindly let me know.
> > 
> > Thanks
> > Kishon
> > 
> > [1] ->
> > https://lore.kernel.org/linux-pci/20191231100331.6316-1-kishon@ti.com/
> > > 
> > > Thanks
> > > Kishon
> > > 
> > > > > 
> > > > > Thanks,
> > > > > Vidya Sagar
> > > > > 
> > > > > On 1/3/20 3:37 PM, Vidya Sagar wrote:
> > > > > > EPC/DesignWare core endpoint subsystems assume that the core
> > > > > > registers are
> > > > > > available always for SW to initialize. But, that may not be the case
> > > > > > always.
> > > > > > For example, Tegra194 hardware has the core running on a clock that
> > > > > > is derived
> > > > > > from reference clock that is coming into the endpoint system from host.
> > > > > > Hence core is made available asynchronously based on when host system
> > > > > > is going
> > > > > > for enumeration of devices. To accommodate this kind of hardwares,
> > > > > > support is
> > > > > > required to defer the core initialization until the respective
> > > > > > platform driver
> > > > > > informs the EPC/DWC endpoint sub-systems that the core is indeed
> > > > > > available for
> > > > > > initiaization. This patch series is attempting to add precisely that.
> > > > > > This series is based on Kishon's patch that adds notification mechanism
> > > > > > support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
> > > > > > 
> > > > > > Vidya Sagar (5):
> > > > > >     PCI: endpoint: Add core init notifying feature
> > > > > >     PCI: dwc: Refactor core initialization code for EP mode
> > > > > >     PCI: endpoint: Add notification for core init completion
> > > > > >     PCI: dwc: Add API to notify core initialization completion
> > > > > >     PCI: pci-epf-test: Add support to defer core initialization
> > > > > > 
> > > > > >    .../pci/controller/dwc/pcie-designware-ep.c   |  79 +++++++-----
> > > > > >    drivers/pci/controller/dwc/pcie-designware.h  |  11 ++
> > > > > >    drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
> > > > > >    drivers/pci/endpoint/pci-epc-core.c           |  19 ++-
> > > > > >    include/linux/pci-epc.h                       |   2 +
> > > > > >    include/linux/pci-epf.h                       |   5 +
> > > > > >    6 files changed, 164 insertions(+), 70 deletions(-)
> > > > > >