From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA79C33CA1 for ; Mon, 20 Jan 2020 09:26:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1093C207FF for ; Mon, 20 Jan 2020 09:26:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726775AbgATJ06 (ORCPT ); Mon, 20 Jan 2020 04:26:58 -0500 Received: from mga09.intel.com ([134.134.136.24]:48234 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726130AbgATJ05 (ORCPT ); Mon, 20 Jan 2020 04:26:57 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jan 2020 01:26:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,341,1574150400"; d="scan'208";a="274639128" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.163]) by fmsmga001.fm.intel.com with SMTP; 20 Jan 2020 01:26:51 -0800 Received: by lahna (sSMTP sendmail emulation); Mon, 20 Jan 2020 11:26:50 +0200 Date: Mon, 20 Jan 2020 11:26:50 +0200 From: Mika Westerberg To: Lee Jones Cc: Andy Shevchenko , Darren Hart , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , x86@kernel.org, Zha Qipeng , "David E . Box" , Guenter Roeck , Heikki Krogerus , Greg Kroah-Hartman , Wim Van Sebroeck , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 35/36] platform/x86: intel_pmc_ipc: Convert to MFD Message-ID: <20200120092650.GI2665@lahna.fi.intel.com> References: <20200113135623.56286-1-mika.westerberg@linux.intel.com> <20200113135623.56286-36-mika.westerberg@linux.intel.com> <20200116132108.GH325@dell> <20200116143730.GE2838@lahna.fi.intel.com> <20200117113202.GH15507@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200117113202.GH15507@dell> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 17, 2020 at 11:32:02AM +0000, Lee Jones wrote: > [...] > > > > Looks like Regmap could save you the trouble here. > > > > Agreed. > > Great. I started to implement regmap for this driver but I run into some problems. The registers we read/write are all 64-bit and accessed trough readq/writeq accessors. However, the regmap API takes unsigned int: int regmap_write(struct regmap *map, unsigned int reg, unsigned int val); int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val); I'm not sure how we can take advantage of this API with the 64-bit registers. There are "raw" versions of the functions that take void pointer like: int regmap_raw_read(struct regmap *map, unsigned int reg, void *val, size_t val_len); but looking at the implementation if the register gets cached it internally does reads in unsigned int sized chunks (if I understand it right). Any ideas how this can be done? Thanks!