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Peter Anvin" , Huang Rui , Janakarajan Natarajan , Jan Beulich , Jiaxun Yang , Jiri Olsa , Josh Poimboeuf , Linus Torvalds , Luwei Kang , =?UTF-8?q?Martin=20Li=C5=A1ka?= , Matt Fleming , Namhyung Kim , Paolo Bonzini , Pawan Gupta , Suravee Suthikulpanit , Thomas Gleixner , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 1/2 v2] perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event map Date: Tue, 21 Jan 2020 11:12:31 -0600 Message-Id: <20200121171232.28839-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.25.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: DM6PR17CA0022.namprd17.prod.outlook.com (2603:10b6:5:1b3::35) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 Received: from fritz.amd.com (165.204.77.1) by DM6PR17CA0022.namprd17.prod.outlook.com (2603:10b6:5:1b3::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2644.20 via Frontend Transport; Tue, 21 Jan 2020 17:12:40 +0000 X-Mailer: git-send-email 2.25.0 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: b1a87a5d-007e-464a-a8ba-08d79e952047 X-MS-TrafficTypeDiagnostic: SN6PR12MB2735:|SN6PR12MB2735: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-Forefront-PRVS: 0289B6431E X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(136003)(376002)(346002)(366004)(396003)(39860400002)(189003)(199004)(54906003)(26005)(478600001)(66946007)(66556008)(36756003)(956004)(110136005)(8936002)(186003)(16526019)(66476007)(6666004)(81166006)(316002)(81156014)(86362001)(966005)(8676002)(1076003)(44832011)(4326008)(5660300002)(2616005)(52116002)(7696005)(2906002)(7416002)(6486002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2735;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Pm4y4RsGgWYD/9xnzLj2fkS1Zrr7/uLXMRuJ1p3glE8hIJriwzhmvinPsBnZtxL+hl3TOMLlG4F+RF319o5/2qP4qMWHI7Gym1iOU3qXNosGF7W6R5NEqQ8NDrx/wX/G70DN7ontR8KRgJatpsPifVOt1t2poV1UcBRwcsVCKB7+FhWAvxThpXmzqksyp0AWB0IDz8uq47/OsPcROUdEa/zhFtH75PboUlLGscnW26BiKOdOnV50AVQLhtlFza+R0xBd+VUnk7j+Tac/CEV+tADb+/Cg/uuUcf/Q4rS+WUeerbj3ChS6ZiNOK1tSXMwIXyUIEgp8dZ6WjhvBOmDvSCsclC+AON9hhqJV6/zG6nkHzVxNwaCVYnWJVhMgwSDBHCjIPaigcJohecohZRLSs2wp8buNr3A79UfXzu2U/Yk70FnrBpi7VUPyw+MAABryhFPsxan/yJRObArKMGWtsy9w2pdFGrJulUWVwGwWulQTlEhkyjI7tftWvt3uKQfwsGr5owDE7YVPGSgcJ2xDUw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b1a87a5d-007e-464a-a8ba-08d79e952047 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2020 17:12:42.6686 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1nmD7zJDoqRB8TdUR56LcIhSmK973ofd1g2T0ZxXNrWAQgjFZUOP+Gj3itHzHFe0vjC67aj3tau2uJ7Tq2uQTQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2735 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h"), claimed L2 misses were unsupported, due to them not being found in its referenced documentation, whose link has now moved [1]. That old documentation listed PMCx064 unit mask bit 3 as: "LsRdBlkC: LS Read Block C S L X Change to X Miss." and bit 0 as: "IcFillMiss: IC Fill Miss" We now have new public documentation [2] with improved descriptions, that clearly indicate what events those unit mask bits represent: Bit 3 now clearly states: "LsRdBlkC: Data Cache Req Miss in L2 (all types)" and bit 0 is: "IcFillMiss: Instruction Cache Req Miss in L2." So we can now add support for L2 misses in perf's genericised events as PMCx064 with both the above unit masks. [1] The commit's original documentation reference, "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", originally available here: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf is now available here: https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf [2] "Processor Programming Reference (PPR) for Family 17h Model 31h, Revision B0 Processors", available here: https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf Cc: Alexander Shishkin Cc: Andi Kleen Cc: Arnaldo Carvalho de Melo Cc: Babu Moger Cc: Borislav Petkov Cc: Fenghua Yu Cc: Frank van der Linden Cc: H. Peter Anvin Cc: Huang Rui Cc: Ingo Molnar Cc: Ingo Molnar Cc: Janakarajan Natarajan Cc: Jan Beulich Cc: Jiaxun Yang Cc: Jiri Olsa Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Luwei Kang Cc: Martin Liška Cc: Matt Fleming Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Pawan Gupta Cc: Peter Zijlstra Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: Tom Lendacky Cc: x86@kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Reported-by: Babu Moger Tested-by: Babu Moger Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h") Signed-off-by: Kim Phillips --- v2: no changes. arch/x86/events/amd/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 1f22b6bbda68..39eb276d0277 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -250,6 +250,7 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, -- 2.25.0