From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24D5AC33CB2 for ; Tue, 28 Jan 2020 14:14:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EBE672468A for ; Tue, 28 Jan 2020 14:14:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1580220845; bh=JEZ3jSxxdzA5cJfhC2uxLflsC5h08bDwll3Dtk7S2PE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=q5nMbgVDrrcx9A6pLqo6V9wcaxB7bxM/DyFpvyT/5Y7KNdwPZpDsJzId2hWvAtPY0 A4D1vAuCozo8LiI0MB8cOMaNIDIdQVUTv8lkoDK2qoKXn/8/szjW6PL8RUVYyEru8N G+yMDBxSLVQN1HGzUltNDahj9NAKGX+ZsOhe6vMA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729789AbgA1OOE (ORCPT ); Tue, 28 Jan 2020 09:14:04 -0500 Received: from mail.kernel.org ([198.145.29.99]:35882 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729199AbgA1OOB (ORCPT ); Tue, 28 Jan 2020 09:14:01 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4D1732468A; Tue, 28 Jan 2020 14:14:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1580220840; bh=JEZ3jSxxdzA5cJfhC2uxLflsC5h08bDwll3Dtk7S2PE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FBzPq/prPS4ySj9wjtUbqR4o/mvoUYY9Qe6PBlXmKEf8i9xq/GivPIAdqf5O/Ar9a Jq5RJJ6qLG5cu0Y5vJSQ8gcimNZ8qTi/0Ts+FONBoYfqeJeMnQEw/2XnbcVw1WA4OR lYLG/87r1aZz+b2uDCbjgWe0pyQOEx9jwt/cvlbo= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= , Adrian Hunter , Ulf Hansson Subject: [PATCH 4.4 169/183] mmc: sdhci: fix minimum clock rate for v3 controller Date: Tue, 28 Jan 2020 15:06:28 +0100 Message-Id: <20200128135846.644221930@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200128135829.486060649@linuxfoundation.org> References: <20200128135829.486060649@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Michał Mirosław commit 2a187d03352086e300daa2044051db00044cd171 upstream. For SDHCIv3+ with programmable clock mode, minimal clock frequency is still base clock / max(divider). Minimal programmable clock frequency is always greater than minimal divided clock frequency. Without this patch, SDHCI uses out-of-spec initial frequency when multiplier is big enough: mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz [for 480 MHz source clock divided by 1024] The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode. Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode") Cc: # 4f6aa3264af4: mmc: tegra: Only advertise UHS modes if IO regulator is present Cc: Signed-off-by: Michał Mirosław Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/sdhci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3096,11 +3096,13 @@ int sdhci_add_host(struct sdhci_host *ho if (host->ops->get_min_clock) mmc->f_min = host->ops->get_min_clock(host); else if (host->version >= SDHCI_SPEC_300) { - if (host->clk_mul) { - mmc->f_min = (host->max_clk * host->clk_mul) / 1024; + if (host->clk_mul) max_clk = host->max_clk * host->clk_mul; - } else - mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; + /* + * Divided Clock Mode minimum clock rate is always less than + * Programmable Clock Mode minimum clock rate. + */ + mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; } else mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;