From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Hans de Goede <hdegoede@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
vipul kumar <vipulk0511@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
linux-kernel@vger.kernel.org, Stable <stable@vger.kernel.org>,
Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>,
Cedric Hombourger <Cedric_Hombourger@mentor.com>,
x86@kernel.org, Len Brown <len.brown@intel.com>,
Vipul Kumar <vipul_kumar@mentor.com>
Subject: Re: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC
Date: Wed, 29 Jan 2020 16:14:44 +0200 [thread overview]
Message-ID: <20200129141444.GE32742@smile.fi.intel.com> (raw)
In-Reply-To: <0d361322-87aa-af48-492c-e8c4983bb35b@redhat.com>
On Wed, Jan 29, 2020 at 02:21:40PM +0100, Hans de Goede wrote:
> On 29-01-2020 14:03, Andy Shevchenko wrote:
> > On Tue, Jan 28, 2020 at 11:39:28PM +0100, Thomas Gleixner wrote:
> > > Hans de Goede <hdegoede@redhat.com> writes:
...
> > > Typical crystal frequencies are 19.2, 24 and 25Mhz.
> >
> > Hans, I think Cherrytrail may be affected by this as the others.
> > CHT AFAIK uses 19.2MHz xtal.
>
> Are you sure?
I'm not. I may mixed this with PMC clock.
> The first 5 entries of the CHT MSR_FSB_FREQ documentation exactly
> match those of the BYT documentation (which has only 5 entries),
> which suggests to me that CHT is also using a 25 MHz crystal.
>
> I can also make the other CHT only frequencies when assuming a 25
> MHz crystal, here is a bit from the patch I'm working on for this:
>
> /*
> * Cherry Trail SDM MSR_FSB_FREQ frequencies to PLL settings map:
> * 0000: 25 * 20 / 6 = 83.3333 MHz
> * 0001: 25 * 4 / 1 = 100.0000 MHz
> * 0010: 25 * 16 / 3 = 133.3333 MHz
> * 0011: 25 * 28 / 6 = 116.6667 MHz
> * 0100: 25 * 16 / 5 = 80.0000 MHz
> * 0101: 25 * 56 / 15 = 93.3333 MHz
> * 0110: 25 * 18 / 5 = 90.0000 MHz
> * 0111: 25 * 32 / 9 = 88.8889 MHz
> * 1000: 25 * 7 / 2 = 87.5000 MHz
> */
>
> The only one which is possibly suspicious here is this line:
>
> * 0111: 25 * 32 / 9 = 88.8889 MHz
>
> The SDM says 88.9 MHz for this one.
Anyway it seems need to be fixed as well.
Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically
it's the same as 10 / 3 and 14 / 3?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-01-29 14:14 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-21 14:41 [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC Vipul Kumar
2020-01-21 15:24 ` Andy Shevchenko
2020-01-21 17:45 ` Thomas Gleixner
[not found] ` <CADdC98RJpsvu_zWehNGDDN=W11rD11NSPaodg-zuaXsHuOJYTQ@mail.gmail.com>
2020-01-22 14:45 ` Thomas Gleixner
[not found] ` <CADdC98TE4oNWZyEsqXzr+zJtfdTTOyeeuHqu1u04X_ktLHo-Hg@mail.gmail.com>
2020-01-23 14:12 ` Thomas Gleixner
2020-01-23 14:41 ` Andy Shevchenko
2020-01-23 21:18 ` Hans de Goede
2020-01-24 8:35 ` Thomas Gleixner
2020-01-24 9:11 ` Hans de Goede
2020-01-24 11:55 ` Thomas Gleixner
2020-01-24 15:54 ` Hans de Goede
[not found] ` <CADdC98To8VKOUWnR+8zAJ04vgdc4vJoh2h96588+5XFer9YTJw@mail.gmail.com>
2020-01-28 14:23 ` Hans de Goede
2020-01-28 14:39 ` vipul kumar
2020-01-28 15:11 ` Thomas Gleixner
2020-01-28 18:57 ` Hans de Goede
2020-01-28 22:39 ` Thomas Gleixner
2020-01-29 13:03 ` Andy Shevchenko
2020-01-29 13:21 ` Hans de Goede
2020-01-29 14:14 ` Andy Shevchenko [this message]
2020-01-29 14:27 ` Hans de Goede
2020-01-29 15:13 ` Thomas Gleixner
2020-01-29 15:53 ` Andy Shevchenko
2020-01-29 15:59 ` Andy Shevchenko
2020-01-29 16:02 ` Andy Shevchenko
2020-01-29 20:57 ` Thomas Gleixner
2020-01-30 8:54 ` Hans de Goede
2020-02-13 18:32 ` Dave Hansen
2020-02-13 21:06 ` Thomas Gleixner
2020-01-29 15:14 ` David Laight
2020-01-29 11:43 ` vipul kumar
2020-01-29 5:20 ` vipul kumar
[not found] ` <20200122022619.B95C024655@mail.kernel.org>
2020-01-22 4:24 ` Kumar, Vipul
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