From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC3EDC35240 for ; Wed, 29 Jan 2020 15:59:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB6F020720 for ; Wed, 29 Jan 2020 15:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726788AbgA2P7O (ORCPT ); Wed, 29 Jan 2020 10:59:14 -0500 Received: from mga09.intel.com ([134.134.136.24]:17283 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726498AbgA2P7O (ORCPT ); Wed, 29 Jan 2020 10:59:14 -0500 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jan 2020 07:59:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,378,1574150400"; d="scan'208";a="223082303" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by fmsmga007.fm.intel.com with ESMTP; 29 Jan 2020 07:59:09 -0800 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1iwpkE-0004JK-Jh; Wed, 29 Jan 2020 17:59:10 +0200 Date: Wed, 29 Jan 2020 17:59:10 +0200 From: Andy Shevchenko To: Thomas Gleixner Cc: Hans de Goede , vipul kumar , Daniel Lezcano , linux-kernel@vger.kernel.org, Stable , Srikanth Krishnakar , Cedric Hombourger , x86@kernel.org, Len Brown , Vipul Kumar Subject: Re: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC Message-ID: <20200129155910.GJ32742@smile.fi.intel.com> References: <87ftg5131x.fsf@nanos.tec.linutronix.de> <30d49be8-67ad-6f32-37a8-0cdd26f0852e@redhat.com> <87sgjz434v.fsf@nanos.tec.linutronix.de> <20200129130350.GD32742@smile.fi.intel.com> <0d361322-87aa-af48-492c-e8c4983bb35b@redhat.com> <20200129141444.GE32742@smile.fi.intel.com> <91cdda7a-4194-ebe7-225d-854447b0436e@redhat.com> <87imku2t3w.fsf@nanos.tec.linutronix.de> <20200129155353.GI32742@smile.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200129155353.GI32742@smile.fi.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 29, 2020 at 05:53:53PM +0200, Andy Shevchenko wrote: > On Wed, Jan 29, 2020 at 04:13:39PM +0100, Thomas Gleixner wrote: > > Hans de Goede writes: > > > On 29-01-2020 15:14, Andy Shevchenko wrote: > > >>> The only one which is possibly suspicious here is this line: > > >>> > > >>> * 0111: 25 * 32 / 9 = 88.8889 MHz > > >>> > > >>> The SDM says 88.9 MHz for this one. > > > > I trust math more than the SDM :) > > > > >> Anyway it seems need to be fixed as well. > > >> > > >> Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically > > >> it's the same as 10 / 3 and 14 / 3? > > > > > > I copied the BYT values from Thomas' email and I guess he did not > > > get around to simplifying them, I'll use the simplified versions > > > for my patch. > > > > Too tired, too lazy :) > > > > Andy, can you please make sure that people inside Intel who can look > > into the secrit documentation confirm what we are aiming for? > > > > Ideally they should provide the X-tal frequency and the mult/div pair > > themself :) > > So, I don't have access to the CPU core documentation (and may be will not be > given), nevertheless I dug a bit to what I have for Cherrytrail. So, the XTAL > is 19.2MHz, which becomes 100MHz and 1600MHz by some root PLL, then, the latter > two frequencies are being used by another PLL to provide a reference clock (*) > to PLL which derives CPU clock. > *) According to colleagues of mine it's a fixed rate source. One more thing. Depends on SKU it may be 400MHz, 320MHz, 200MHz or 333MHz. (I guess these values should be kinda references in the table) > That's all what I have. -- With Best Regards, Andy Shevchenko