From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B86C2D0DB for ; Thu, 30 Jan 2020 21:13:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A61E7214D8 for ; Thu, 30 Jan 2020 21:13:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YztztHo+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727949AbgA3VNK (ORCPT ); Thu, 30 Jan 2020 16:13:10 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46964 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727927AbgA3VNH (ORCPT ); Thu, 30 Jan 2020 16:13:07 -0500 Received: by mail-pg1-f193.google.com with SMTP id z124so2273531pgb.13 for ; Thu, 30 Jan 2020 13:13:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oa49p/xGTn6NCKmNAd8eGM0hUYKRobdCqjFRXtL8/kA=; b=YztztHo+5GQxLT621C7Rqngv72wMhREmQYp/vsbj0VtWWHVT1+KSLTkNKq3nPnnT77 u96ZJxht7JRHvwCE695YNRG5Uha2O2igcMyHdsHpf0hmrv3tbv/L2mWXHlqFgY431VFB sFrWLJFUmpQYg22ekzG2C7G5D1oa04m585Vtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oa49p/xGTn6NCKmNAd8eGM0hUYKRobdCqjFRXtL8/kA=; b=lHMB9+frdyQGGT1rZGr0sXgR4iVlGUSbUJg6lJLh2SMuVFulIpVuXlUy6KbSw59sh/ LZrBVuqDO+pfb6s4Bdze9/iF276IPSN0gfzP4bLJ08R2D9EA/PdkZPP+UC6zmHLptB/M HnhUtD29tP1TM0x0GVzIs/9VEoRQXQQS4Pe9XJrhn0P0IAwx4OFczS8AgSfg8r+cOFRt QOZoDtk9Zrexr5fMv2n2Zv0fIPgZIgMAY/qIvimDUBA0MSFun4JydrnXq07MwIchzdMu ZbmCo7/ishO2ykP2dJLc6akVf2O/3g/gY92eel0SUAW77V0Xhy+RZLXnLqzmwO80L2wH XMVg== X-Gm-Message-State: APjAAAVzdskviMT+K+3DJ4Gttf07iAOc3atlOT/GzKWsp3YntWpX/iYP QR2qtQsPUJmxjcc7b5y+JTJByg== X-Google-Smtp-Source: APXvYqzzw2CG5kff+mpG3Nv7sadrfFm8uoc1EhB2TT6G2I2DqhJX1YdC+8eq25u2MR3IrmdXmtro/w== X-Received: by 2002:a62:1d07:: with SMTP id d7mr6747690pfd.159.1580418786161; Thu, 30 Jan 2020 13:13:06 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id ci5sm4343871pjb.5.2020.01.30.13.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 13:13:05 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v3 15/15] arm64: dts: sc7180: Add clock controller nodes Date: Thu, 30 Jan 2020 13:12:31 -0800 Message-Id: <20200130131220.v3.15.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200130211231.224656-1-dianders@chromium.org> References: <20200130211231.224656-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Taniya Das Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson --- Changes in v3: - Added videocc include file. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Added includes - Changed various parent names to match bindings / driver arch/arm64/boot/dts/qcom/sc7180.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..57ff5e0f7ae6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,8 +5,11 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include +#include #include +#include #include #include #include @@ -1039,6 +1042,20 @@ pinmux { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1151,6 +1168,36 @@ usb_1_dwc3: dwc3@a600000 { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- 2.25.0.341.g760bfbb309-goog