From: Stephen Boyd <sboyd@kernel.org>
To: Rahul Tanwar <rahul.tanwar@linux.intel.com>,
linux-clk@vger.kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, robh+dt@kernel.org, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
andriy.shevchenko@intel.com, qi-ming.wu@intel.com,
yixin.zhu@linux.intel.com, cheol.yong.kim@intel.com,
Rahul Tanwar <rahul.tanwar@linux.intel.com>
Subject: Re: [PATCH v4 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU
Date: Thu, 30 Jan 2020 18:25:40 -0800 [thread overview]
Message-ID: <20200131022541.3853C2067C@mail.kernel.org> (raw)
In-Reply-To: <24933f5f1c48a891f9c05c7292117108fc880932.1580374761.git.rahul.tanwar@linux.intel.com>
Quoting Rahul Tanwar (2020-01-30 01:04:03)
> Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
> Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
> controller driver of LGM.
>
> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
> ---
Please reorder this to be first instead of second in the series.
> .../devicetree/bindings/clock/intel,cgu-lgm.yaml | 40 +++++
> include/dt-bindings/clock/intel,lgm-clk.h | 165 +++++++++++++++++++++
> 2 files changed, 205 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
> create mode 100644 include/dt-bindings/clock/intel,lgm-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
> new file mode 100644
> index 000000000000..e9649fe75435
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/intel,cgu-lgm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
> +
> +maintainers:
> + - Rahul Tanwar <rahul.tanwar@linux.intel.com>
> +
> +description: |
> + Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
> + all means to access the CGU hardware module in order to generate a series
> + of clocks for the whole system and individual peripherals.
Can you include a pointer to include/dt-bindings/clock/intel,lgm-clk.h?
> +
> +properties:
> + compatible:
> + const: intel,cgu-lgm
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +examples:
> + - |
> + cgu: clock-controller@e0200000 {
> + compatible = "intel,cgu-lgm";
> + reg = <0xe0200000 0x33c>;
> + #clock-cells = <1>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/intel,lgm-clk.h b/include/dt-bindings/clock/intel,lgm-clk.h
> new file mode 100644
> index 000000000000..d6797521d36a
> --- /dev/null
> +++ b/include/dt-bindings/clock/intel,lgm-clk.h
[...]
> +
> +/* PLL0CZ */
> +#define LGM_CLK_CM 25
> +#define LGM_CLK_IC 26
> +#define LGM_CLK_SDXC3 27
> +
> +/* PLL0B */
> +#define LGM_CLK_NGI 30
> +#define LGM_CLK_NOC4 31
> +#define LGM_CLK_SW 32
> +#define LGM_CLK_QSPI 33
> +#define LGM_CLK_CQEM LGM_CLK_SW
> +#define LGM_CLK_EMMC5 LGM_CLK_NOC4
> +
> +/* PLL1 */
> +#define LGM_CLK_CT 35
> +#define LGM_CLK_DSP 36
> +#define LGM_CLK_VIF 37
> +
> +/* LJPLL3 */
> +#define LGM_CLK_CML 40
> +#define LGM_CLK_SERDES 41
> +#define LGM_CLK_POOL 42
> +#define LGM_CLK_PTP 43
> +
> +/* LJPLL4 */
> +#define LGM_CLK_PCIE 45
> +#define LGM_CLK_SATA LGM_CLK_PCIE
What is with the aliases?
next prev parent reply other threads:[~2020-01-31 2:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-30 9:04 [PATCH v4 0/2] clk: intel: Add a new driver for a new clock controller IP Rahul Tanwar
2020-01-30 9:04 ` [PATCH v4 1/2] clk: intel: Add CGU clock driver for a new SoC Rahul Tanwar
2020-01-31 2:24 ` Stephen Boyd
2020-02-13 8:04 ` Tanwar, Rahul
2020-01-30 9:04 ` [PATCH v4 2/2] dt-bindings: clk: intel: Add bindings document & header file for CGU Rahul Tanwar
2020-01-31 2:25 ` Stephen Boyd [this message]
2020-02-05 9:10 ` Tanwar, Rahul
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