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[178.15.117.54]) by smtp.gmail.com with ESMTPSA id c13sm539929wrx.9.2020.02.06.12.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 12:24:40 -0800 (PST) From: shiva.linuxworks@gmail.com X-Google-Original-From: sshivamurthy@micron.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Frieder Schrempf , Boris Brezillon , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Shivamurthy Shastri Subject: [PATCH v4 5/5] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies Date: Thu, 6 Feb 2020 21:22:06 +0100 Message-Id: <20200206202206.14770-6-sshivamurthy@micron.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200206202206.14770-1-sshivamurthy@micron.com> References: <20200206202206.14770-1-sshivamurthy@micron.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shivamurthy Shastri Add device table for new Micron SPI NAND devices, which have multiple dies. Also, enable support to select the dies. Signed-off-by: Shivamurthy Shastri --- drivers/mtd/nand/spi/micron.c | 58 +++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 3d3734afc35e..84e1c109ad0c 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -20,6 +20,15 @@ #define MICRON_CFG_CONTI_READ BIT(0) +/* + * As per datasheet, die selection is done by the 6th bit of Die + * Select Register (Address 0xD0). + */ +#define MICRON_DIE_SELECT_REG 0xD0 + +#define MICRON_SELECT_DIE_0 0x00 +#define MICRON_SELECT_DIE_1 0x40 + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -66,6 +75,22 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .free = micron_8_ooblayout_free, }; +static int micron_select_target(struct spinand_device *spinand, + unsigned int target) +{ + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, + spinand->scratchbuf); + + if (target == 0) + *spinand->scratchbuf = MICRON_SELECT_DIE_0; + else if (target == 1) + *spinand->scratchbuf = MICRON_SELECT_DIE_1; + else + return -EINVAL; + + return spi_mem_exec_op(spinand->spimem, &op); +} + static int micron_8_ecc_get_status(struct spinand_device *spinand, u8 status) { @@ -133,6 +158,17 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M79A 4Gb 3.3V */ + SPINAND_INFO("MT29F4G01ADAGD", 0x36, + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 4Gb 3.3V */ SPINAND_INFO("MT29F4G01ABAFD", 0x34, NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -153,6 +189,28 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), + /* M70A 8Gb 3.3V */ + SPINAND_INFO("MT29F8G01ADAFD", 0x46, + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), + /* M70A 8Gb 1.8V */ + SPINAND_INFO("MT29F8G01ADBFD", 0x47, + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_CR_FEAT_BIT, + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), }; static int micron_spinand_detect(struct spinand_device *spinand) -- 2.17.1