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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r3sm253200pfg.145.2020.02.06.12.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 12:33:39 -0800 (PST) Date: Thu, 6 Feb 2020 12:33:36 -0800 From: Bjorn Andersson To: Can Guo Cc: asutoshd@codeaurora.org, nguyenb@codeaurora.org, hongwus@codeaurora.org, rnayak@codeaurora.org, linux-scsi@vger.kernel.org, kernel-team@android.com, saravanak@google.com, salyzyn@google.com, Andy Gross , Alim Akhtar , Avri Altman , "James E.J. Bottomley" , "Martin K. Petersen" , "open list:ARM/QUALCOMM SUPPORT" , open list Subject: Re: [PATCH v7 7/8] scsi: ufs-qcom: Delay specific time before gate ref clk Message-ID: <20200206203336.GQ2514@yoga> References: <1580978008-9327-1-git-send-email-cang@codeaurora.org> <1580978008-9327-8-git-send-email-cang@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1580978008-9327-8-git-send-email-cang@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 06 Feb 00:33 PST 2020, Can Guo wrote: > After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait > time is required before disable the device reference clock. If it is not > specified, use the old delay. > > Signed-off-by: Can Guo > Reviewed-by: Asutosh Das > Reviewed-by: Hongwu Su > --- > drivers/scsi/ufs/ufs-qcom.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c > index 85d7c17..39eefa4 100644 > --- a/drivers/scsi/ufs/ufs-qcom.c > +++ b/drivers/scsi/ufs/ufs-qcom.c > @@ -833,6 +833,8 @@ static int ufs_qcom_bus_register(struct ufs_qcom_host *host) > > static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) > { > + unsigned long gating_wait; > + > if (host->dev_ref_clk_ctrl_mmio && > (enable ^ host->is_dev_ref_clk_enabled)) { > u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); > @@ -845,11 +847,25 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) > /* > * If we are here to disable this clock it might be immediately > * after entering into hibern8 in which case we need to make > - * sure that device ref_clk is active at least 1us after the > + * sure that device ref_clk is active for specific time after > * hibern8 enter. > */ > - if (!enable) > - udelay(1); > + if (!enable) { > + gating_wait = host->hba->dev_info.clk_gating_wait_us; > + if (!gating_wait) { Afaict this can't happen, because in patch 6 you check for gating_wait being 0 and if so set it to 0xff. > + udelay(1); > + } else { > + /* > + * bRefClkGatingWaitTime defines the minimum > + * time for which the reference clock is > + * required by device during transition from > + * HS-MODE to LS-MODE or HIBERN8 state. Give it > + * more time to be on the safe side. > + */ > + gating_wait += 10; > + usleep_range(gating_wait, gating_wait + 10); I presume there's no strong requirement on the max, so how about using a substantially larger max - say 1k, or 10k - to allow the usleep_range() to do it's job? PS. Please include linux-arm-msm@ on all the patches in the series, not just two of them. Regards, Bjorn > + } > + } > > writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project