From: Will Deacon <email@example.com> To: Wu Hao <firstname.lastname@example.org> Cc: email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org, Luwei Kang <email@example.com> Subject: Re: [PATCH v7 2/2] fpga: dfl: fme: add performance reporting support Date: Mon, 10 Feb 2020 16:34:01 +0000 [thread overview] Message-ID: <20200210163400.GA21900@willie-the-truck> (raw) In-Reply-To: <firstname.lastname@example.org> Hi, On Mon, Feb 10, 2020 at 11:47:49AM +0800, Wu Hao wrote: > This patch adds support for performance reporting private feature > for FPGA Management Engine (FME). Now it supports several different > performance counters, including 'basic', 'cache', 'fabric', 'vtd' > and 'vtd_sip'. It allows user to use standard linux tools to access > these performance counters. I had a quick look at this, and it mostly looks alright to me. Just a few high-level comments/questions: - I would still prefer for the PMU drivers to live under drivers/perf/ - You should probably give the PMU a better name than "fme%d", for example "intel_fpga_dfl_fme%d". - CPU0 can be hotplugged off on non-x86 systems. How do you cope with that? - readq() will emit 2x32-bit reads on some architectures. What happens in this case? Will
next prev parent reply other threads:[~2020-02-10 16:34 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-10 3:47 [PATCH v7 0/2] add performance reporting support to FPGA DFL drivers Wu Hao 2020-02-10 3:47 ` [PATCH v7 1/2] Documentation: fpga: dfl: add description for performance reporting support Wu Hao 2020-02-10 3:47 ` [PATCH v7 2/2] fpga: dfl: fme: add " Wu Hao 2020-02-10 16:34 ` Will Deacon [this message] 2020-02-12 3:19 ` Wu Hao 2020-02-12 5:30 ` Greg KH 2020-02-12 10:02 ` Wu Hao 2020-02-12 13:20 ` Greg KH 2020-02-13 2:51 ` Wu Hao 2020-02-10 20:56 ` Greg KH 2020-02-12 2:39 ` Wu Hao
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