From: Peter Zijlstra <peterz@infradead.org>
To: Michal Simek <michal.simek@xilinx.com>
Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com,
arnd@arndb.de, Stefan Asserhall <stefan.asserhall@xilinx.com>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>
Subject: Re: [PATCH 6/7] microblaze: Implement architecture spinlock
Date: Wed, 12 Feb 2020 16:47:56 +0100 [thread overview]
Message-ID: <20200212154756.GY14897@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <ed53474e9ca6736353afd10ebe7ea98e4c6c459e.1581522136.git.michal.simek@xilinx.com>
On Wed, Feb 12, 2020 at 04:42:28PM +0100, Michal Simek wrote:
> From: Stefan Asserhall <stefan.asserhall@xilinx.com>
>
> Using exclusive loads/stores to implement spinlocks which can be used on
> SMP systems.
>
> Signed-off-by: Stefan Asserhall <stefan.asserhall@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++++
> arch/microblaze/include/asm/spinlock_types.h | 25 ++
> 2 files changed, 265 insertions(+)
> create mode 100644 arch/microblaze/include/asm/spinlock.h
> create mode 100644 arch/microblaze/include/asm/spinlock_types.h
>
> diff --git a/arch/microblaze/include/asm/spinlock.h b/arch/microblaze/include/asm/spinlock.h
> new file mode 100644
> index 000000000000..0199ea9f7f0f
> --- /dev/null
> +++ b/arch/microblaze/include/asm/spinlock.h
> @@ -0,0 +1,240 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2013-2020 Xilinx, Inc.
> + */
> +
> +#ifndef _ASM_MICROBLAZE_SPINLOCK_H
> +#define _ASM_MICROBLAZE_SPINLOCK_H
> +
> +/*
> + * Unlocked value: 0
> + * Locked value: 1
> + */
> +#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
> +
> +static inline void arch_spin_lock(arch_spinlock_t *lock)
> +{
> + unsigned long tmp;
> +
> + __asm__ __volatile__ (
> + /* load conditional address in %1 to %0 */
> + "1: lwx %0, %1, r0;\n"
> + /* not zero? try again */
> + " bnei %0, 1b;\n"
> + /* increment lock by 1 */
> + " addi %0, r0, 1;\n"
> + /* attempt store */
> + " swx %0, %1, r0;\n"
> + /* checking msr carry flag */
> + " addic %0, r0, 0;\n"
> + /* store failed (MSR[C] set)? try again */
> + " bnei %0, 1b;\n"
> + /* Outputs: temp variable for load result */
> + : "=&r" (tmp)
> + /* Inputs: lock address */
> + : "r" (&lock->lock)
> + : "cc", "memory"
> + );
> +}
That's a test-and-set spinlock if I read it correctly. Why? that's the
worst possible spinlock implementation possible.
next prev parent reply other threads:[~2020-02-12 15:48 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-12 15:42 [PATCH 0/7] microblaze: Define SMP safe operations Michal Simek
2020-02-12 15:42 ` [PATCH 1/7] microblaze: timer: Don't use cpu timer setting Michal Simek
2020-02-12 15:42 ` [PATCH 2/7] microblaze: Make cpuinfo structure SMP aware Michal Simek
2020-02-12 20:42 ` Arnd Bergmann
2020-02-12 15:42 ` [PATCH 3/7] microblaze: Define SMP safe bit operations Michal Simek
2020-02-12 15:53 ` Peter Zijlstra
2020-02-13 8:42 ` Michal Simek
2020-02-13 9:01 ` Stefan Asserhall
2020-02-13 9:11 ` Peter Zijlstra
2020-02-13 9:24 ` Stefan Asserhall
2020-02-12 15:42 ` [PATCH 4/7] microblaze: Add SMP implementation of xchg and cmpxchg Michal Simek
2020-02-12 15:42 ` [PATCH 5/7] microblaze: Remove disabling IRQ while pte_update() run Michal Simek
2020-02-12 15:42 ` [PATCH 6/7] microblaze: Implement architecture spinlock Michal Simek
2020-02-12 15:47 ` Peter Zijlstra [this message]
2020-02-13 7:51 ` Michal Simek
2020-02-13 8:00 ` Peter Zijlstra
2020-02-12 15:42 ` [PATCH 7/7] microblaze: Do atomic operations by using exclusive ops Michal Simek
2020-02-12 15:55 ` Peter Zijlstra
2020-02-13 8:06 ` Michal Simek
2020-02-13 8:58 ` Peter Zijlstra
2020-02-13 9:16 ` Peter Zijlstra
2020-02-13 10:04 ` Will Deacon
2020-02-13 10:14 ` Stefan Asserhall
2020-02-13 10:20 ` Will Deacon
2020-02-13 10:15 ` Peter Zijlstra
2020-02-13 11:34 ` Boqun Feng
2020-02-13 11:38 ` Boqun Feng
2020-02-13 13:51 ` Andrea Parri
2020-02-13 14:01 ` Andrea Parri
2020-02-12 16:08 ` [PATCH 0/7] microblaze: Define SMP safe operations Peter Zijlstra
2020-02-12 16:38 ` Peter Zijlstra
2020-02-13 7:49 ` Michal Simek
2020-02-13 8:11 ` Peter Zijlstra
2020-02-13 8:12 ` Michal Simek
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