From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26807C3B1B5 for ; Fri, 14 Feb 2020 18:12:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E428724688 for ; Fri, 14 Feb 2020 18:12:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581703932; bh=Gq5rf7u/9z+VyLshbO6znJXsbmBI15OFp5FIdk80igY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=qnyD5xBLNS6HGUNN4CG9pOjP2aY9RylxPO47sWFwLY2JPY43LknNpekyVvt+ySBxm PN2ujhaWBD9e0eaLgerhC7rNZzXF8POLIUdoKDRvCyvfnwOXV7ZhOFhuRhbRX4o30l 7SAlFQ9xNZXrr+1WAQSk1hHbM3PtuqQjN7G/Jhv4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731184AbgBNPxO (ORCPT ); Fri, 14 Feb 2020 10:53:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:59958 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731089AbgBNPwz (ORCPT ); Fri, 14 Feb 2020 10:52:55 -0500 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CB9BE24676; Fri, 14 Feb 2020 15:52:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581695574; bh=Gq5rf7u/9z+VyLshbO6znJXsbmBI15OFp5FIdk80igY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hpcJGucVxt8jaP/sMHgE9Mqw/lrKlpBMU9xswbR8NBIKsN+XsXGrUAoJaYU0bNt4g Y4k7gaJcUS18EJEb87Xh3A4hPcAqzOy+h0CHaGctkbFu83lKdHT/z1M2EpRxd0dYEi PhxvX/Y3jdIL9NFYB2NpE43nAXD7bA6yBU5iZjUs= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Andre Przywara , Maxime Ripard , Sasha Levin , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.5 185/542] arm: dts: allwinner: H3: Add PMU node Date: Fri, 14 Feb 2020 10:42:57 -0500 Message-Id: <20200214154854.6746-185-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214154854.6746-1-sashal@kernel.org> References: <20200214154854.6746-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andre Przywara [ Upstream commit 0388a110747bec0c9d9de995842bb2a03a26aae1 ] Add the Performance Monitoring Unit (PMU) device tree node to the H3 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on an OrangePi Zero. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin --- arch/arm/boot/dts/sun8i-h3.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index fe773c72a69b7..b4f1673df9ee0 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -80,7 +80,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; @@ -90,7 +90,7 @@ #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; @@ -100,7 +100,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -111,6 +111,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , -- 2.20.1