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Thu, 20 Feb 2020 09:23:50 -0800 (PST) Date: Thu, 20 Feb 2020 17:23:48 +0000 From: Andrew Murray To: Zhiqiang Hou Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, andrew.murray@arm.com, arnd@arndb.de, mark.rutland@arm.com, l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org, m.karthikeyan@mobiveil.co.in, leoyang.li@nxp.com, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Mingkai.Hu@nxp.com, Minghuan.Lian@nxp.com, Xiaowei.Bao@nxp.com Subject: Re: [PATCHv10 03/13] PCI: mobiveil: Collect the interrupt related operations into a function Message-ID: <20200220172348.GF19388@big-machine> References: <20200213040644.45858-1-Zhiqiang.Hou@nxp.com> <20200213040644.45858-4-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200213040644.45858-4-Zhiqiang.Hou@nxp.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 13, 2020 at 12:06:34PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang > > Collect the interrupt initialization related operations into > a new function such that it is more readable. > > Signed-off-by: Hou Zhiqiang Reviewed-by: Andrew Murray > --- > V10: > - Refined the subject and change log. > > drivers/pci/controller/pcie-mobiveil.c | 65 +++++++++++++++++--------- > 1 file changed, 42 insertions(+), 23 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index 01df04ea5b48..9449528bb14f 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -454,12 +454,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) > return PTR_ERR(pcie->csr_axi_slave_base); > pcie->pcie_reg_base = res->start; > > - /* map MSI config resource */ > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); > - pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); > - if (IS_ERR(pcie->apb_csr_base)) > - return PTR_ERR(pcie->apb_csr_base); > - > /* read the number of windows requested */ > if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) > pcie->apio_wins = MAX_PIO_WINDOWS; > @@ -467,12 +461,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) > if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) > pcie->ppio_wins = MAX_PIO_WINDOWS; > > - rp->irq = platform_get_irq(pdev, 0); > - if (rp->irq <= 0) { > - dev_err(dev, "failed to map IRQ: %d\n", rp->irq); > - return -ENODEV; > - } > - > return 0; > } > > @@ -618,9 +606,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); > mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); > > - mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), > - PAB_INTP_AMBA_MISC_ENB); > - > /* > * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in > * PAB_AXI_PIO_CTRL Register > @@ -670,9 +655,6 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > value |= (PCI_CLASS_BRIDGE_PCI << 16); > mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); > > - /* setup MSI hardware registers */ > - mobiveil_pcie_enable_msi(pcie); > - > return 0; > } > > @@ -873,6 +855,46 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) > return 0; > } > > +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) > +{ > + struct platform_device *pdev = pcie->pdev; > + struct device *dev = &pdev->dev; > + struct mobiveil_root_port *rp = &pcie->rp; > + struct resource *res; > + int ret; > + > + /* map MSI config resource */ > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr"); > + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); > + if (IS_ERR(pcie->apb_csr_base)) > + return PTR_ERR(pcie->apb_csr_base); > + > + /* setup MSI hardware registers */ > + mobiveil_pcie_enable_msi(pcie); > + > + rp->irq = platform_get_irq(pdev, 0); > + if (rp->irq <= 0) { > + dev_err(dev, "failed to map IRQ: %d\n", rp->irq); > + return -ENODEV; > + } > + > + /* initialize the IRQ domains */ > + ret = mobiveil_pcie_init_irq_domain(pcie); > + if (ret) { > + dev_err(dev, "Failed creating IRQ Domain\n"); > + return ret; > + } > + > + irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); > + > + /* Enable interrupts */ > + mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), > + PAB_INTP_AMBA_MISC_ENB); > + > + > + return 0; > +} > + > static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) > { > struct mobiveil_root_port *rp = &pcie->rp; > @@ -906,15 +928,12 @@ static int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) > return ret; > } > > - /* initialize the IRQ domains */ > - ret = mobiveil_pcie_init_irq_domain(pcie); > + ret = mobiveil_pcie_interrupt_init(pcie); > if (ret) { > - dev_err(dev, "Failed creating IRQ Domain\n"); > + dev_err(dev, "Interrupt init failed\n"); > return ret; > } > > - irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); > - > /* Initialize bridge */ > bridge->dev.parent = dev; > bridge->sysdata = pcie; > -- > 2.17.1 >