From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE9E6C35669 for ; Sun, 23 Feb 2020 02:32:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B957620659 for ; Sun, 23 Feb 2020 02:32:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582425162; bh=DRIj/511LI9YCCerkUGQuQURMrZ2X0geKBW/bOYrSwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=hEyxRMHWOOxAmVbuODIkY/dM0RSD8B7rAPwlUilvUVMhUiOAPtnuegol4nAfPbXm4 ZkyoE5prPGAc7xp6TLEVekH2VKYceAsuRDZqY42+V45BqB1l0g0R42Ha5oQFu6nwpr XLj2G/inUUFN0c0eUmhJzaqK6gpSwq9USKgaTTWo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727706AbgBWCXK (ORCPT ); Sat, 22 Feb 2020 21:23:10 -0500 Received: from mail.kernel.org ([198.145.29.99]:52306 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728421AbgBWCXG (ORCPT ); Sat, 22 Feb 2020 21:23:06 -0500 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 981A8208C4; Sun, 23 Feb 2020 02:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582424585; bh=DRIj/511LI9YCCerkUGQuQURMrZ2X0geKBW/bOYrSwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tT6I7qmb96XSR3nffMDZSi2LZ4+V6HpLkjGiMqs9sonosk4dGQZG/2z/8k26SC9zl QGlbS5eN6rbJuUdlLe6m2FyhEBsHrm3f23T3c6mMHdf7C5XI/s0lyctf8mMfRnXZtx 4O2hnIiOs01xNzWdH0AyHp8aSqVAl6VKVkXZi92I= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Yongqiang Sun , Eric Yang , Bhawanpreet Lakha , Alex Deucher , Sasha Levin , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.4 24/50] drm/amd/display: Limit minimum DPPCLK to 100MHz. Date: Sat, 22 Feb 2020 21:22:09 -0500 Message-Id: <20200223022235.1404-24-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200223022235.1404-1-sashal@kernel.org> References: <20200223022235.1404-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yongqiang Sun [ Upstream commit 6c81917a0485ee2a1be0dc23321ac10ecfd9578b ] [Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by: Yongqiang Sun Reviewed-by: Eric Yang Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 787f94d815f42..dd92f9c295b45 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -91,6 +91,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; + } + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; -- 2.20.1