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Mon, 2 Mar 2020 18:07:50 +0000 From: To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 09/23] mtd: spi-nor: Move Everspin bits out of core.c Thread-Topic: [PATCH 09/23] mtd: spi-nor: Move Everspin bits out of core.c Thread-Index: AQHV8L18TK41hD+gVUGQ55J4iGg1rA== Date: Mon, 2 Mar 2020 18:07:49 +0000 Message-ID: <20200302180730.1886678-10-tudor.ambarus@microchip.com> References: <20200302180730.1886678-1-tudor.ambarus@microchip.com> In-Reply-To: <20200302180730.1886678-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1c6ca503-0991-4a9c-00cd-08d7bed49eb8 x-ms-traffictypediagnostic: MN2PR11MB4142: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; x-forefront-prvs: 033054F29A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(39860400002)(136003)(396003)(376002)(189003)(199004)(36756003)(26005)(66446008)(107886003)(6486002)(186003)(2616005)(4326008)(478600001)(6512007)(91956017)(64756008)(66946007)(2906002)(71200400001)(76116006)(8936002)(316002)(86362001)(54906003)(6506007)(66556008)(5660300002)(66476007)(7406005)(1076003)(7416002)(81156014)(81166006)(110136005)(8676002);DIR:OUT;SFP:1101;SCL:1;SRVR:MN2PR11MB4142;H:MN2PR11MB4448.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: m9+BgFAYTRd92e1ANJXjBLdI6XmFC8Wt0bBqM5+d+luVH33LeGFdu+Jfkb1E2y7/ftIFW0W6JbdqiewF8wRBjGICW2KCzX9JRJw/StBV2lErW2dRUARPjD43gAyXKgnbOJaNfIWlatCy8HUHJ/nwCNdi+ezOuTMB5zzfPc/uMjxfoMhEPQ80oO03mYlb5qwigz+FlzOvwGXuAd7XZj08dsSX3d2OW61DI2H+i7yujnEc1iDEn7YkDhWlyd3z7YfGW2hXFCW0wJsXPDlpM7WLhwetWwdbnhpHXh+cgd+mtZmBN+wLKJgs8ZV528mZmujipbtO67Ke6fvsq6fF1fMkEqdl/bHpVd3ezoB7iPeQybepiGYyMv7Z4anj4ikzStj/PEsHlwH+gTkiq9hAbfbsI1jtkCe0gZr/afbQ+jjqfSFP2EatrASErlconsrWLcMl x-ms-exchange-antispam-messagedata: Sg02pV9zz9o0tr+QvXXUrc1RXHiaBXfUCoc9HyRFvZPxdkKFFVfd17Gka3kq03oACReIyBzVsaIKGotJN/G+qnyM1y6BHx2ggjshfiFG/6ps14ksxR0q4CnINHG2tOl7PvfJ4cYsLIy2YlMmNy6hWQ== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1c6ca503-0991-4a9c-00cd-08d7bed49eb8 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Mar 2020 18:07:50.0118 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Abhsjg48ZATt41Obr4fbzEwsPVdTHKzvXacQP1lKRdZsOLZGLSAmjphNfiV6TAV55bgQFhN4K0e0lCUJpbPXrSyI9fldo2C7Br/nK+DnIrg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4142 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon Create a SPI NOR manufacturer driver for Everspin chips, and move the Everspin definitions outside of core.c. Signed-off-by: Boris Brezillon Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/core.c | 7 +------ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/everspin.c | 27 +++++++++++++++++++++++++++ 4 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 drivers/mtd/spi-nor/everspin.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 4e5ef10e4fd7..384c520689d8 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -4,4 +4,5 @@ spi-nor-objs :=3D core.o sfdp.o spi-nor-objs +=3D atmel.o spi-nor-objs +=3D eon.o spi-nor-objs +=3D esmt.o +spi-nor-objs +=3D everspin.o obj-$(CONFIG_MTD_SPI_NOR) +=3D spi-nor.o diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 30a0ddc6de81..07eec3476053 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2079,12 +2079,6 @@ static struct spi_nor_fixups gd25q256_fixups =3D { * old entries may be missing 4K flag. */ static const struct flash_info spi_nor_ids[] =3D { - /* Everspin */ - { "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NO= R_NO_FR) }, - { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NO= R_NO_FR) }, - { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NO= R_NO_FR) }, - { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NO= R_NO_FR) }, - /* Fujitsu */ { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, =20 @@ -2435,6 +2429,7 @@ static const struct spi_nor_manufacturer *manufacture= rs[] =3D { &spi_nor_atmel, &spi_nor_eon, &spi_nor_esmt, + &spi_nor_everspin, }; =20 static const struct flash_info * diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 23ce99fb8087..d36e7f93dbcf 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -170,6 +170,7 @@ struct spi_nor_manufacturer { extern const struct spi_nor_manufacturer spi_nor_atmel; extern const struct spi_nor_manufacturer spi_nor_eon; extern const struct spi_nor_manufacturer spi_nor_esmt; +extern const struct spi_nor_manufacturer spi_nor_everspin; =20 int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.= c new file mode 100644 index 000000000000..04a177a32283 --- /dev/null +++ b/drivers/mtd/spi-nor/everspin.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2005, Intec Automation Inc. + * Copyright (C) 2014, Freescale Semiconductor, Inc. + */ + +#include + +#include "core.h" + +static const struct flash_info everspin_parts[] =3D { + /* Everspin */ + { "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2, + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, + { "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2, + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, + { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, + { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, + SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, +}; + +const struct spi_nor_manufacturer spi_nor_everspin =3D { + .name =3D "everspin", + .parts =3D everspin_parts, + .nparts =3D ARRAY_SIZE(everspin_parts), +}; --=20 2.23.0