From: Viresh Kumar <viresh.kumar@linaro.org>
To: peng.fan@nxp.com
Cc: shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
Anson.Huang@nxp.com, linux-pm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API
Date: Tue, 3 Mar 2020 11:15:47 +0530 [thread overview]
Message-ID: <20200303054547.4wpnzmgnuo7jd2qa@vireshk-i7> (raw)
In-Reply-To: <1583201690-16068-1-git-send-email-peng.fan@nxp.com>
On 03-03-20, 10:14, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Use nvmem API is better compared with direclty accessing OCOTP registers.
> nvmem could handle OCOTP clk, defer probe.
>
> Patch 1/3 is dts changes to add nvmem related properties
> Patch 2/3 is a bug fix
> Patch 3/3 is convert to nvmem API
Should I apply patch 2 and 3 ? And you can take 1/3 via ARM Soc tree
as this shouldn't break anything.
--
viresh
next prev parent reply other threads:[~2020-03-03 5:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 2:14 [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API peng.fan
2020-03-03 2:14 ` [PATCH 1/3] ARM: dts: imx: add nvmem property for cpu0 peng.fan
2020-03-11 8:30 ` Shawn Guo
2020-03-03 2:14 ` [PATCH 2/3] cpufreq: imx6q: fix error handling peng.fan
2020-03-03 2:14 ` [PATCH 3/3] cpufreq: imx6q: read OCOTP through nvmem for imx6q peng.fan
2020-03-03 5:45 ` Viresh Kumar [this message]
2020-03-03 6:16 ` [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API Peng Fan
2020-03-03 11:17 ` Viresh Kumar
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