From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98877C3F2D1 for ; Tue, 3 Mar 2020 15:03:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A0692083E for ; Tue, 3 Mar 2020 15:03:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729071AbgCCPDu (ORCPT ); Tue, 3 Mar 2020 10:03:50 -0500 Received: from foss.arm.com ([217.140.110.172]:48408 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727851AbgCCPDu (ORCPT ); Tue, 3 Mar 2020 10:03:50 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75598101E; Tue, 3 Mar 2020 07:03:49 -0800 (PST) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8F1493F6C4; Tue, 3 Mar 2020 07:03:47 -0800 (PST) Date: Tue, 3 Mar 2020 15:03:45 +0000 From: Lorenzo Pieralisi To: Kevin Hilman Cc: Remi Pommarel , Kishon Vijay Abraham I , Yue Wang , Bjorn Helgaas , Neil Armstrong , Martin Blumenstingl , Rob Herring , Jerome Brunet , linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v6 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Message-ID: <20200303150345.GB6334@e121166-lin.cambridge.arm.com> References: <20200123232943.10229-1-repk@triplefau.lt> <20200224141549.GB15614@e121166-lin.cambridge.arm.com> <7h8sklbcmo.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7h8sklbcmo.fsf@baylibre.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Feb 29, 2020 at 05:07:43PM +0100, Kevin Hilman wrote: > Lorenzo Pieralisi writes: > > > On Fri, Jan 24, 2020 at 12:29:36AM +0100, Remi Pommarel wrote: > >> PCIe device probing failures have been seen on AXG platforms and were > >> due to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit > >> in MIPI's PHY registers solved the problem. This bit controls band gap > >> reference. > >> > >> As discussed here [1] one of these shared MIPI/PCIE analog PHY register > >> bits was implemented in the clock driver as CLKID_MIPI_ENABLE. This adds > >> a PHY driver to control this bit instead, as well as setting the band > >> gap one in order to get reliable PCIE communication. > >> > >> While at it add another PHY driver to control PCIE only PHY registers, > >> making AXG code more similar to G12A platform thus allowing to remove > >> some specific platform handling in pci-meson driver. > >> > >> Please note that CLKID_MIPI_ENABLE removable will be done in a different > >> serie. > >> > >> Changes since v5: > >> - Add additionalProperties in device tree binding documentation > >> - Make analog PHY required > >> > >> Changes since v4: > >> - Rename the shared MIPI/PCIe PHY to analog > >> - Chain the MIPI/PCIe PHY to the PCIe one > >> > >> Changes since v3: > >> - Go back to the shared MIPI/PCIe phy driver solution from v2 > >> - Remove syscon usage > >> - Add all dt-bindings documentation > >> > >> Changes since v2: > >> - Remove shared MIPI/PCIE device driver and use syscon to access register > >> in PCIE only driver instead > >> - Include devicetree documentation > >> > >> Changes sinve v1: > >> - Move HHI_MIPI_CNTL0 bit control in its own PHY driver > >> - Add a PHY driver for PCIE_PHY registers > >> - Modify pci-meson.c to make use of both PHYs and remove specific > >> handling for AXG and G12A > >> > >> [1] https://lkml.org/lkml/2019/12/16/119 > >> > >> Remi Pommarel (7): > >> dt-bindings: Add AXG PCIE PHY bindings > >> dt-bindings: Add AXG shared MIPI/PCIE analog PHY bindings > >> dt-bindings: PCI: meson: Update PCIE bindings documentation > >> arm64: dts: meson-axg: Add PCIE PHY nodes > >> phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver > >> phy: amlogic: Add Amlogic AXG PCIE PHY Driver > >> PCI: amlogic: Use AXG PCIE > >> > >> .../bindings/pci/amlogic,meson-pcie.txt | 22 +- > >> .../amlogic,meson-axg-mipi-pcie-analog.yaml | 35 ++++ > >> .../bindings/phy/amlogic,meson-axg-pcie.yaml | 52 +++++ > >> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 16 ++ > >> drivers/pci/controller/dwc/pci-meson.c | 116 ++--------- > >> drivers/phy/amlogic/Kconfig | 22 ++ > >> drivers/phy/amlogic/Makefile | 12 +- > >> .../amlogic/phy-meson-axg-mipi-pcie-analog.c | 188 +++++++++++++++++ > >> drivers/phy/amlogic/phy-meson-axg-pcie.c | 192 ++++++++++++++++++ > >> 9 files changed, 543 insertions(+), 112 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml > >> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml > >> create mode 100644 drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c > >> create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c > > > > Hi Remi, > > > > I am ready to pull this series in, do you want me to ? Or you prefer > > it to go via a different tree upstream ? > > To avoid conflicts, I'll take the DT patch (PATCH 4/7) through my > amlogic tree, but feel free to take the rest. That works for me Kevin, thanks ! Lorenzo