From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <andrew.murray@arm.com>
Cc: <kishon@ti.com>, <gustavo.pimentel@synopsys.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V5 1/5] soc/tegra: bpmp: Update ABI header
Date: Tue, 3 Mar 2020 23:40:48 +0530 [thread overview]
Message-ID: <20200303181052.16134-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20200303181052.16134-1-vidyas@nvidia.com>
Update the firmware header to support uninitialization of UPHY PLL
when the PCIe controller is operating in endpoint mode and host cuts
the PCIe reference clock.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V5:
* None
V4:
* None
V3:
* Added Acked-by: Thierry Reding <treding@nvidia.com>
V2:
* Changed Copyright year from 2019 to 2020
include/soc/tegra/bpmp-abi.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
index cac6f610b3fe..8f8e73e5cd45 100644
--- a/include/soc/tegra/bpmp-abi.h
+++ b/include/soc/tegra/bpmp-abi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _ABI_BPMP_ABI_H_
@@ -2119,6 +2119,7 @@ enum {
CMD_UPHY_PCIE_LANE_MARGIN_STATUS = 2,
CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3,
CMD_UPHY_PCIE_CONTROLLER_STATE = 4,
+ CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF = 5,
CMD_UPHY_MAX,
};
@@ -2151,6 +2152,11 @@ struct cmd_uphy_pcie_controller_state_request {
uint8_t enable;
} __ABI_PACKED;
+struct cmd_uphy_ep_controller_pll_off_request {
+ /** @brief EP controller number, valid: 0, 4, 5 */
+ uint8_t ep_controller;
+} __ABI_PACKED;
+
/**
* @ingroup UPHY
* @brief Request with #MRQ_UPHY
@@ -2165,6 +2171,7 @@ struct cmd_uphy_pcie_controller_state_request {
* |CMD_UPHY_PCIE_LANE_MARGIN_STATUS | |
* |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request |
* |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request |
+ * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF |cmd_uphy_ep_controller_pll_off_request |
*
*/
@@ -2178,6 +2185,7 @@ struct mrq_uphy_request {
struct cmd_uphy_margin_control_request uphy_set_margin_control;
struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init;
struct cmd_uphy_pcie_controller_state_request controller_state;
+ struct cmd_uphy_ep_controller_pll_off_request ep_ctrlr_pll_off;
} __UNION_ANON;
} __ABI_PACKED;
--
2.17.1
next prev parent reply other threads:[~2020-03-03 18:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 18:10 [PATCH V5 0/5] Add support for PCIe endpoint mode in Tegra194 Vidya Sagar
2020-03-03 18:10 ` Vidya Sagar [this message]
2020-03-03 18:10 ` [PATCH V5 2/5] dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes " Vidya Sagar
2020-03-03 18:10 ` [PATCH V5 3/5] arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 Vidya Sagar
2020-03-03 18:10 ` [PATCH V5 4/5] arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform Vidya Sagar
2020-03-03 18:10 ` [PATCH V5 5/5] PCI: tegra: Add support for PCIe endpoint mode in Tegra194 Vidya Sagar
2020-03-22 14:50 ` Guenter Roeck
2020-03-22 17:15 ` Vidya Sagar
2020-03-30 21:47 ` Bjorn Helgaas
2020-03-31 2:55 ` Vidya Sagar
2020-03-31 3:00 ` Bjorn Helgaas
2020-03-31 8:23 ` Lorenzo Pieralisi
2020-03-31 15:25 ` Bjorn Helgaas
2020-03-11 10:52 ` [PATCH V5 0/5] " Lorenzo Pieralisi
2020-03-11 14:30 ` Thierry Reding
2020-03-11 15:48 ` Vidya Sagar
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