Re: [PATCH] PCI/PM: Skip link training delay for S3 resume

From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: bhelgaas@google.com, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI/PM: Skip link training delay for S3 resume
Date: Thu, 12 Mar 2020 10:04:24 +0200	[thread overview]
Message-ID: <20200312080424.GH2540@lahna.fi.intel.com> (raw)
In-Reply-To: <2C20385C-4BA4-4D6D-935A-AFDB97FAB5ED@canonical.com>

On Thu, Mar 12, 2020 at 12:23:46PM +0800, Kai-Heng Feng wrote:
> Hi,
> 
> > On Mar 11, 2020, at 18:28, Mika Westerberg <mika.westerberg@linux.intel.com> wrote:
> > 
> > Hi,
> > 
> > On Wed, Mar 11, 2020 at 12:52:49PM +0800, Kai-Heng Feng wrote:
> >> Commit ad9001f2f411 ("PCI/PM: Add missing link delays required by the
> >> PCIe spec") added a 1100ms delay on resume for bridges that don't
> >> support Link Active Reporting.
> >> 
> >> The commit also states that the delay can be skipped for S3, as the
> >> firmware should already handled the case for us.
> > 
> > Delay can be skipped if the firmware provides _DSM with function 8
> > implemented according to PCI firmwre spec 3.2 sec 4.6.8.
> 
> As someone who doesn't have access to the PCI spec...
> Questions below.
> 
> > 
> >> So let's skip the link training delay for S3, to save 1100ms resume
> >> time.
> >> 
> >> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
> >> ---
> >> drivers/pci/pci-driver.c | 3 ++-
> >> 1 file changed, 2 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
> >> index 0454ca0e4e3f..3050375bad04 100644
> >> --- a/drivers/pci/pci-driver.c
> >> +++ b/drivers/pci/pci-driver.c
> >> @@ -916,7 +916,8 @@ static int pci_pm_resume_noirq(struct device *dev)
> >> 	pci_fixup_device(pci_fixup_resume_early, pci_dev);
> >> 	pcie_pme_root_status_cleanup(pci_dev);
> >> 
> >> -	if (!skip_bus_pm && prev_state == PCI_D3cold)
> >> +	if (!skip_bus_pm && prev_state == PCI_D3cold
> >> +	    && !pm_resume_via_firmware())
> > 
> > So this would need to check for the _DSM result as well. We do evaluate
> > it in pci_acpi_optimize_delay() (drivers/pci/pci-acpi.c) and that ends
> > up lowering ->d3cold_delay so maybe check that here.
> 
> Do we need to wait for d3cold_delay here?
> Or we can also skip that as long as pci_acpi_dsm_guid and FUNCTION_DELAY_DSM present?

Actually I think pci_bridge_wait_for_secondary_bus() already takes it
into account. Have you checked if the BIOS has this _DSM implemented in
the first place?