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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id d3sm55113197pfn.113.2020.03.12.17.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 17:01:49 -0700 (PDT) Date: Thu, 12 Mar 2020 17:01:47 -0700 From: Kees Cook To: Mark Brown Cc: Catalin Marinas , Will Deacon , Alexander Viro , Paul Elliott , Peter Zijlstra , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , Marc Zyngier , Eugene Syromiatnikov , Szabolcs Nagy , "H . J . Lu " , Andrew Jones , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Thomas Gleixner , Florian Weimer , Sudakshina Das , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-fsdevel@vger.kernel.org, Dave Martin Subject: Re: [PATCH v9 13/13] arm64: BTI: Add Kconfig entry for userspace BTI Message-ID: <202003121700.9260E027@keescook> References: <20200311192608.40095-1-broonie@kernel.org> <20200311192608.40095-14-broonie@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200311192608.40095-14-broonie@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 11, 2020 at 07:26:08PM +0000, Mark Brown wrote: > From: Dave Martin > > Now that the code for userspace BTI support is in the kernel add the > Kconfig entry so that it can be built and used. > > [Split out of "arm64: Basic Branch Target Identification support" -- > broonie] > > Signed-off-by: Dave Martin Reviewed-by: Kees Cook -Kees > Signed-off-by: Mark Brown > --- > arch/arm64/Kconfig | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 8a15bc68dadd..d65d226a77ec 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1522,6 +1522,28 @@ endmenu > > menu "ARMv8.5 architectural features" > > +config ARM64_BTI > + bool "Branch Target Identification support" > + default y > + help > + Branch Target Identification (part of the ARMv8.5 Extensions) > + provides a mechanism to limit the set of locations to which computed > + branch instructions such as BR or BLR can jump. > + > + To make use of BTI on CPUs that support it, say Y. > + > + BTI is intended to provide complementary protection to other control > + flow integrity protection mechanisms, such as the Pointer > + authentication mechanism provided as part of the ARMv8.3 Extensions. > + For this reason, it does not make sense to enable this option without > + also enabling support for pointer authentication. Thus, when > + enabling this option you should also select ARM64_PTR_AUTH=y. > + > + Userspace binaries must also be specifically compiled to make use of > + this mechanism. If you say N here or the hardware does not support > + BTI, such binaries can still run, but you get no additional > + enforcement of branch destinations. > + > config ARM64_E0PD > bool "Enable support for E0PD" > default y > -- > 2.20.1 > -- Kees Cook